Semiconductor device having resistance based memory array, method of reading, and systems associated therewith
First Claim
1. A semiconductor device, comprising:
- a non-volatile memory cell array, memory cells of the non-volatile memory cell array being resistance based, and each memory cell having a resistance that changes over time after data is written into the memory cell;
a write address buffer configured to store write addresses associated with data being written into the non-volatile memory cell array; and
a read unit configured to perform a read operation to read data from the non-volatile memory cell array, the read unit configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array.
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Accused Products
Abstract
In one embodiment, the semiconductor device includes a non-volatile memory cell array. Memory cells of the non-volatile memory cell array are resistance based, and each memory cell has a resistance that changes over time after data is written into the memory cell. A write address buffer is configured to store write addresses associated with data being written into the non-volatile memory cell array, and a read unit is configured to perform a read operation to read data from the non-volatile memory cell array. The read unit is configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array.
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Citations
40 Claims
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1. A semiconductor device, comprising:
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a non-volatile memory cell array, memory cells of the non-volatile memory cell array being resistance based, and each memory cell having a resistance that changes over time after data is written into the memory cell; a write address buffer configured to store write addresses associated with data being written into the non-volatile memory cell array; and a read unit configured to perform a read operation to read data from the non-volatile memory cell array, the read unit configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A semiconductor device, comprising:
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a non-volatile memory cell array, memory cells of the non-volatile memory cell array being resistance based, and each memory cell having a resistance that changes over time after data is written into the memory cell; a write address buffer configured to store write addresses associated with data being written into the non-volatile memory cell array; and a read unit configured to perform a read operation to read data from the non-volatile memory cell array, the read unit configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of an amount of time since data was written into the non-volatile memory cell array.
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38. A card, comprising:
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a memory, the memory including, a non-volatile memory cell array, memory cells of the non-volatile memory cell array being resistance based, and each memory cell having a resistance that changes over time after data is written into the memory cell; a write address buffer configured to store write addresses associated with data being written into the non-volatile memory cell array; and a read unit configured to perform a read operation to read data from the non-volatile memory cell array, the read unit configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array; and a control unit configured to control the memory.
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39. A system, comprising:
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a bus; a semiconductor device connected to the bus, the semiconductor device including, a non-volatile memory cell array, memory cells of the non-volatile memory cell array being resistance based, and each memory cell having a resistance that changes over time after data is written into the memory cell; a write address buffer configured to store write addresses associated with data being written into the non-volatile memory cell array; and a read unit configured to perform a read operation to read data from the non-volatile memory cell array, the read unit configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array; and an input/output device connected to the bus; and a processor connected to the bus, the processor configured to communicate with the input/output device and the semiconductor device via the bus.
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40. A method of reading data from a semiconductor device, comprising:
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storing data being written into the non-volatile memory cell array in a write buffer; storing write addresses associated with data being written into the non-volatile memory cell array; and controlling a read current applied to the non-volatile memory cell array during a read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array.
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Specification