MEMORY STRUCTURE HAVING VOLATILE AND NON-VOLATILE MEMORY PORTIONS

• US 20090237996A1
• Filed: 03/20/2008
• Published: 09/24/2009
• Est. Priority Date: 03/20/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kirsch, Howard C., Ingalls, Charles, Juengling, Werner
• Granted Patent: US 7,898,857 B2
• Time in Patent Office: Days
• US Class Current: 365/185.80
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.

Claims

1. A device, comprising:

a transistor comprising;

a first gate switchably coupled to a first signal that is configured to turn on the transistor;

a second gate switchably coupled to a second signal that is configured to turn on the transistor,

wherein the first gate is coupled to a non-volatile memory.

2. The device of claim 1, wherein the transistor is a field effect transistor.

3. The device of claim 1, comprising a fin disposed between the first gate and the second gate.

4. The device of claim 3, wherein the fin comprises a source, a drain, a channel, and a dielectric portion that extends through a width of the fin, the dielectric portion disposed between the source and the drain and adjacent to at least part of the channel.

5. The device of claim 1, wherein the transistor comprises a first layer comprising a gate oxide, a second layer, and a third layer comprising a gate oxide, wherein the first layer, second layer, and third layer are disposed adjacent to at least a portion of the channel and interposed between at least part of the source and at least part of the drain and interposed between at least part of the first gate.

6. The device of claim 5, wherein the second layer comprises silicon nitride, nanoparticles, or a combination thereof.

7. The device of claim 1, wherein the non-volatile memory comprises a charge storage node.

8. The device of claim 7, wherein the non-volatile memory comprises SONOS memory.

9. The device of claim 1, wherein the second gate is coupled to a volatile memory.

10. The device of claim 9, wherein the volatile memory comprises a capacitive element.

11. The device of claim 10, wherein the capacitive element is disposed on a drain of the transistor.

12. A device comprising:

a memory array comprising;

a memory cell comprising;

a volatile memory portion; and

a non-volatile memory portion,

wherein the volatile memory portion and the non-volatile memory portion share a source, a drain, and a body of a transistor.

13. The device of claim 12, comprising a dataline coupled to the source of the transistor.

14. A method of operating a memory array, comprising:

reading data from one of a non-volatile memory portion of a memory cell or a non-volatile portion of a memory cell; and

writing the data to the other portion of the memory cell, wherein the volatile memory portion and non-volatile memory portion of the memory cell share a source, a drain, and a body of a transistor.

15. The method of claim 14, wherein reading data from a row of the volatile memory portions comprises applying a voltage to a gate coupled to the volatile memory portions of the memory cell.

16. The method of claim 14, comprising erasing the non-volatile memory portion of the memory cell prior to writing the data to the non-volatile memory portion of the memory cell.

17. The method of claim 16, wherein the erasing is initiated by a signal indicating a change in a system using the memory array.

18. The method of claim 14, wherein writing the data comprises applying a voltage to a gate coupled to the non-volatile memory portion of the memory cell.

19. The method of claim 18, comprising applying the voltage to a second gate coupled to a non-volatile memory portion of a second memory cell such that charge is trapped in the non-volatile memory portion of the memory cell but not the non-volatile memory portion of the second memory cell.

20. The method of claim 14, wherein reading data from the non-volatile memory portion of the memory cell comprises applying a voltage to a gate coupled to the non-volatile memory portion of the memory cell.

21. The method of claim 14, wherein reading data from the non-volatile memory portion of the memory cell comprises using a DRAM capacitor to read a flash memory cell.

22. The method of claim 20, wherein the voltage activates the non-volatile memory portion of the memory cell if the non-volatile memory portion comprises a low threshold voltage.

23. The method of claim 14, wherein reading comprises precharging one or more datalines of the memory array.

24. A method of operating a memory array, comprising:

reading data from volatile memory portions of a first row of memory cells;

writing the data to volatile memory portions of a second row of memory cells; and

erasing non-volatile memory portions of the first row of memory cells.

25. The method of claim 24, wherein erasing the non-volatile memory portions of the first row of memory cells comprises lowering a voltage applied to gate coupled to the non-volatile memory portions of the first row of memory cells.

26. The method of claim 25, wherein erasing comprises activating at least one of a plurality of datalines of the memory array.

27. The method of claim 24, comprising reading data from the volatile memory portions of the second row of memory cells and writing the data to the volatile memory portions of the first row of memory cells.

28. A method of operating a memory array, comprising:

transferring data from non-volatile memory portions of a row of memory cells to volatile memory portions of the row of memory cells;

erasing the non-volatile memory portions of the row of memory cells; and

transferring data from the volatile memory portions of the row of memory cells to the non-volatile memory portions of the row of memory cells,

wherein the non-volatile memory portion and the volatile memory portion of each memory cell share a source, a drain, and a body of a transistor.

29. The method of claim 28, wherein the non-volatile memory portions comprise charge storage node.

30. The method of claim 28, wherein the non-volatile memory portions comprise SONOS memory.

31. The method of claim 28, wherein the volatile memory portions comprises a capacitive element.

32. A method of operating a memory array, comprising:

activating a first plurality of rows of the memory array, wherein each of the rows are electrically isolated from each other, wherein an active row of the first plurality of rows does not interfere with another active row of the first plurality of rows, wherein the memory array comprises a plurality of rows of memory cells having non-volatile memory portions and volatile memory portions, wherein the non-volatile memory portion and the volatile memory portion of each memory cell share a source, a drain, and a body.

33. The method of claim 32, comprising electrically isolating the plurality of rows via a sense module.

34. The method of claim 32, comprising activating a plurality of sense amplifiers such that at least 50% of a plurality of datalines coupled to the plurality of sense amplifiers and the plurality of rows are active.

35. The method of claim 32, comprising activating a second plurality of rows of the memory array, wherein each of the rows are electrically isolated from each other, such that an active row of the second plurality of rows does not interfere with another active row of the second plurality of rows and the first plurality of rows.

36. A device, comprising:

a fin-shaped semiconductor;

a first layer disposed on a side of the semiconductor, wherein the first layer comprises a first gate oxide; and

a second layer disposed on a side of the semiconductor, the second layer comprising a second gate oxide, a third gate oxide, and a charge storage layer disposed between the second gate oxide and the third gate oxide.

37. The device of claim 36, comprising a first conductor disposed on the first layer.

38. The device of claim 37, comprising a second conductor disposed on the second layer.

39. The device of claim 36, wherein the fin-shaped semiconductor comprises a plurality of field effect transistors, where each field effect transistor comprises a source and a gate.

40. The device of claim 39, wherein the first layer is configured to allow operation of a plurality of volatile memory portions coupled to the plurality of field effect transistors.

41. The device of claim 40, wherein the plurality of volatile memory portions comprises a plurality of capacitive elements disposed on the drains of the plurality of field effect transistors.

42. The device of claim 39, wherein the source and drain of each of the plurality of field effect transistors are separated by a trench.

43. The device of claim 42, wherein the trench comprises a dielectric.