NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20090238003A1
• Filed: 02/02/2009
• Published: 09/24/2009
• Est. Priority Date: 02/14/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shimizu, Yuui, NAMIKI, Yuko, Futatsuyama, Takuya
• Granted Patent: US 7,965,555 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.

Claims

1. A non-volatile semiconductor memory device comprising:

a NAND string, in which a plurality of memory cells are connected in series and first and second select gate transistors are disposed on the both ends for coupling them to a bit line and a source line, respectively;

a plurality of word lines coupled to the respective control gates of the memory cells; and

first and second select gate lines coupled to the gates of the first and second select gate transistors, respectively, wherein

a data read mode is defined by the following bias condition;

a selected word line is applied with a read voltage;

one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side of the selected word line is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and

second unselected word lines disposed on the second select gate line side of the selected word line are applied with a third read pass voltage higher than the first read voltage.

2. The non-volatile semiconductor memory device according to claim 1, wherein

in case the selected word line is one nearest to the first select gate line in the data read mode, the whole unselected word lines are applied with the third read pass voltage.

3. The non-volatile semiconductor memory device according to claim 1, wherein

in case the selected word line is one nearest to the second select gate line in the data read mode, one adjacent to the selected word line within the first unselected word lines is applied with the first read pass voltage while the others are applied with the second read pass voltage.

4. The non-volatile semiconductor memory device according to claim 1, wherein

the NAND string further includes a first dummy cell disposed between the first select gate transistor and the neighboring memory cell;

and a second dummy cell disposed between the second select gate transistor and the neighboring memory cell, the control gates of the first and second dummy cells being coupled to first and second dummy word lines, respectively, and wherein

in the data read mode, the first dummy word line is applied with the second read pass voltage while the second dummy word line is applied with the third read pass voltage.

5. The non-volatile semiconductor memory device according to claim 1, wherein

the NAND string further includes a first dummy cell disposed between the first select gate transistor and the neighboring memory cell;

and a second dummy cell disposed between the second select gate transistor and the neighboring memory cell, the control gates of the first and second dummy cells being coupled to first and second dummy word lines, respectively, and wherein

in the data read mode, the first dummy word line is applied with a fourth read pass voltage lower than the second read pass voltage while the second dummy word line is applied with the first read pass voltage.

6. The non-volatile semiconductor memory device according to claim 1, wherein

the data read mode is a verify-read mode in a data write sequence.

7. A non-volatile semiconductor memory device comprising:

a NAND string, in which a plurality of memory cells are connected in series and first and second select gate transistors are disposed on the both ends for coupling them to a bit line and a source line, respectively;

a plurality of word lines coupled to the respective control gates of the memory cells; and

first and second select gate lines coupled to the gates of the first and second select gate transistors, respectively, wherein

a data read mode is defined by the following bias condition;

a selected word line is applied with a read voltage;

one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side of the selected word line is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and

second unselected word lines disposed on the second select gate line side of the selected word line are applied with the first read pass voltage.

8. The non-volatile semiconductor memory device according to claim 7, wherein

the NAND string further includes a first dummy cell disposed between the first select gate transistor and the neighboring memory cell;

and a second dummy cell disposed between the second select gate transistor and the neighboring memory cell, the control gates of the first and second dummy cells being coupled to first and second dummy word lines, respectively, and wherein

in the data read mode, the first dummy word line is applied with the second read pass voltage while the second dummy word line is applied with the first read pass voltage.

9. The non-volatile semiconductor memory device according to claim 7, wherein

the NAND string further includes a first dummy cell disposed between the first select gate transistor and the neighboring memory cell;

and a second dummy cell disposed between the second select gate transistor and the neighboring memory cell, the control gates of the first and second dummy cells being coupled to first and second dummy word lines, respectively, and wherein

in the data read mode, the first dummy word line is applied with a fourth read pass voltage lower than the second read voltage while the second dummy word line is applied with the first read pass voltage.

10. The non-volatile semiconductor memory device according to claim 7, wherein

the data read mode is a verify-read mode in a data write sequence.

11. A non-volatile semiconductor memory device comprising:

a NAND string, in which a plurality of memory cells are connected in series and first and second select gate transistors are disposed on the both ends for coupling them to a bit line and a source line, respectively;

a plurality of word lines coupled to the respective control gates of the memory cells; and

first and second select gate lines coupled to the gates of the first and second select gate transistors, respectively, wherein

a data read mode is defined by the following bias condition;

a selected word line is applied with a read voltage;

one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side of the selected word line is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and

one adjacent to the selected word line within second unselected word lines disposed on the second select gate line side of the selected word line are applied with third read pass voltage higher than the first read pass voltage while the others are applied with the first read pass voltage.

12. The non-volatile semiconductor memory device according to claim 11, wherein

the NAND string further includes a first dummy cell disposed between the first select gate transistor and the neighboring memory cell;

and a second dummy cell disposed between the second select gate transistor and the neighboring memory cell, the control gates of the first and second dummy cells being coupled to first and second dummy word lines, respectively, and wherein

in the data read mode, the first dummy word line is applied with the second read pass voltage while the second dummy word line is applied with the first read pass voltage.

13. The non-volatile semiconductor memory device according to claim 11, wherein

the NAND string further includes a first dummy cell disposed between the first select gate transistor and the neighboring memory cell;

and a second dummy cell disposed between the second select gate transistor and the neighboring memory cell, the control gates of the first and second dummy cells being coupled to first and second dummy word lines, respectively, and wherein

in the data read mode, the first dummy word line is applied with a fourth read pass voltage lower than the second read voltage while the second dummy word line is applied with the first read pass voltage.

14. The non-volatile semiconductor memory device according to claim 11, wherein

the data read mode is a verify-read mode in a data write sequence.