MULTI-PLANE TYPE FLASH MEMORY AND METHODS OF CONTROLLING PROGRAM AND READ OPERATIONS THEREOF

• US 20090238005A1
• Filed: 05/28/2009
• Published: 09/24/2009
• Est. Priority Date: 03/10/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: YOU, Byoung Sung
• Granted Patent: US 8,347,042 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A multi-plane type flash memory device comprises a plurality of planes each including a plurality of memory cell blocks, page buffers each latching an input data bit to be output to its corresponding plane or latching an output data bit to be received from the corresponding plane, cache buffers each storing an input or output data bits in response to one of cache input control signals and each transferring the stored data bit to the page buffer or an external device in response to one of cache output control signals, and a control logic circuit generating the cache input and output control signals in response to command and chip enable signals containing plural bits. The program and read operations for the plural planes are conducted simultaneously in response to the chip enable signal containing the plural bits, which increases an operation speed and data throughput processed therein.

Claims

1. A flash memory device comprising:

a control logic circuit to generate cache input control signals, cache output control signals and chip enable signals having a plurality of bit signals, wherein;

the cache input control signals correspond to the bit signals,

each cache input control signal is generated when a corresponding bit signal changes from a high level to a low level,

the control logic circuit receives addresses when the bit signals are at a low level,

the cache input control signals are generated in sequence during a program operation or are simultaneously generated during a read operation, and

the cache output control signals are simultaneously generated in the program operation or are generated in sequence in the read operation;

a plurality of planes each including a plurality of memory cell blocks, wherein;

the number of planes corresponds to the number of bit signals of each chip enable signal, and

in the program operation, data is simultaneously programmed in each of the plurality of planes based on the corresponding bit signals;

a plurality of page buffers, each page buffer arranged in correspondence with one of the planes, each page buffer simultaneously latching an input data bit to be output to its corresponding plane or simultaneously latching an output data bit to be received from the corresponding plane; and

a plurality of cache buffers, each cache buffer being arranged in correspondence with one of the page buffers and the corresponding plane, wherein;

in the read operation, the data programmed in the plurality of planes is simultaneously output to the plurality of cache buffers based on the corresponding bit signals,

the cache buffers store in sequence the input data bits in response to the cache input control signals in the program operation or simultaneously store the latched output data bits in response to the cache input control signals in the read operation, and

the cache buffers simultaneously transfer the stored data bits to the corresponding page buffers in response to the cache output control signals in the program operation or transfer the stored data bits in sequence to an external device in response to the cache output control signals in the read operation.

2. The flash memory device as set forth in claim 1, wherein the control logic circuit generates one among a program command, a read command, and an erase command in response to the command signal, and generates row and column address signals in response to an external address signal.

3. The flash memory device as set forth in claim 1, wherein the number of the bit signals for each chip enable signal is identical to the number of the planes.

4. The flash memory device as set forth in claim 2, further comprising:

a high voltage generator generating bias voltages in response to one among the program voltage, the read command, and the erase command;

an X-decoder selecting one of the memory cell blocks included in each of the planes on basis of the row address signal and supplying the bias voltages to the selected memory cell block; and

a Y-decoder decoding the column address signal and applying the column address signal to the page buffers,

wherein the page buffers select bitlines of corresponding planes partially or entirely in response to the column decoding signal, and output the input data bits to the selected bitlines or latch the output data bits received from the selected bitlines.

5. The flash memory device as set forth in claim 2, wherein the control logic circuit generates the program command when the command signal contains a page program setup code, and disables a ready/busy signal for a first predetermined time when receiving the command signal containing a confirmation code after generating the program command.

6. The flash memory device as set forth in claim 5, wherein the control logic circuit, after generating the program command, enables the cache input control signals one by one in sequence for a second predetermined time when the bit signals are changed into a predetermined logic value one by one in sequence for the second predetermined time, and enables the cache output control signals at the same time while the ready/busy signal is being disabled when the bit signals are changed into the predetermined logic value at the same time for the first predetermined time, and

wherein the cache buffers store the input data bits one by one in sequence when the cache input control signals are enabled one by one in sequence, and outputs the stored data bits to the page buffers at the same time when the cache output control signals are enabled at the same time.

7. The flash memory device as set forth in claim 6, wherein after storing the input data bits stored in the last one of the cache buffers, the bit signals are changed to the predetermined logic value at the same time for the first predetermined time.

8. The flash memory device as set forth in claim 2, wherein the control logic circuit generates the read command when the command signal contains a read code, and disables a ready/busy signal for a first predetermined time when the external address signal is received after generating the read command.

9. The flash memory device as set forth in claim 8, wherein the control logic circuit, after generating the read command, enables the cache input control signals at the same time while the ready/busy signal is being disabled, and enables the cache output control signals one by one in sequence for a second predetermined time when the bit signals are changed into a predetermined logic value one by one in sequence for the second predetermined time, and

wherein the cache buffers store the latched output data bits received from the page buffers when the cache input control signals are enabled at the same time, and output the stored data bits to the external device one by one in sequence when the cache output control signals are enabled one by one in sequence.

10. The flash memory device as set forth in claim 9, wherein the bit signals are changed into the predetermined logic value when the control logic circuit receives the command signal, being maintained in the predetermined logic value when the ready/busy signal is being disabled.

11. The flash memory device as set forth in claim 9, wherein the bit signals are changed into the predetermined logic value one by one in sequence for the second predetermined time after the latched output data bits are sequentially stored in the cache buffers.

12. A method of controlling a program operation of a multi-plane type flash memory device, the method comprising:

generating a program command in response to a command signal;

receiving addresses when a plurality of chip enable signals having a plurality of bit signals change to a low level;

storing input data bits into cache buffers arranged in correspondence with a plurality of planes, wherein;

the number of planes corresponds to the number of bit signals,

each plane comprises a plurality of memory blocks, and

the cache buffers operate in sequence in response to cache input control signals which are enabled in sequence in the program operation;

generating bias voltages for the program operation in response to the program command;

selecting one of the memory cell blocks of each of the planes according to row and column address signals which are generated by the addresses;

applying the bias voltages to the selected memory cell blocks;

simultaneously outputting data bits stored in the cache buffers to page buffers of the planes in response to cache output control signals which are simultaneously enabled in the program operation; and

simultaneously programming the data bits from the page buffers to the selected memory cell blocks based on the corresponding bit signals.

13. The method as set forth in claim 12, wherein the storing-input-data-bits step comprises:

enabling the cache input control signals one by one in sequence for a predetermined time in response to the chip enable signals;

storing the input data bits in a corresponding one of the cache buffers in response to one of the cache input control signals; and

repeating the enabling-cache-input-control-signals step and storing-the-input-data-bits step until the input data bits are stored up to the last one of the cache buffers.

14. The method as set forth in claim 13, wherein the enabling step comprises:

changing the bit signals of the chip enable signals into a predetermined logic value one by one in sequence for the predetermined time after generation of the program command.

15. The method as set forth in claim 13, wherein the storing-input-data-bits step further comprises:

changing the bit signals of the chip enable signals into a predetermined logic value simultaneously for a predetermined time after the input data bits are stored up to the last one of the cache buffers.

16. The method as set forth in claim 12, wherein the outputting step comprises:

enabling cache output control signals simultaneously, when the bit signals of the chip enable signals are changed into a predetermined logic value simultaneously for a first predetermined time and for a second predetermined time after generation of the program command;

outputting data bits stored in the cache buffers to the page buffers that are each coupled to at least one of the cache buffers and arranged in correspondence with the plurality of planes, in response to the cache output control signals; and

latching the stored data bits in the page buffers and outputting the latched data bits each to the plurality of planes.

17. A method of controlling a read operation of a multi-plane type flash memory device, the method comprising:

generating a read command in response to a command signal;

receiving addresses when a plurality of chip enable signals having a plurality of bit signals change to a low level;

generating bias voltages for the read operation in response to the read command;

selecting one memory cell block of a plurality of memory cell blocks from each of a plurality of planes, wherein;

the number of planes corresponding to the number of bit signals, and

each of the memory cell blocks are selected according to row and column address signals which are generated by the addresses;

applying the bias voltages to the selected memory cell blocks;

simultaneously outputting data bits programmed in the selected memory cell blocks of the planes based on the corresponding bit signals;

storing the output data bits of the planes simultaneously in cache buffers arranged in correspondence with the planes in response to cache input control signals which are simultaneously enabled during the read operation; and

outputting the data bits stored in the cache buffers to an external device one by one in sequence in response to cache output control signals which are enabled in sequence during the read operation.

18. The method as set forth in claim 17, wherein the storing step comprises:

latching the output data bits in page buffers arranged in correspondence with the planes;

enabling cache input control signals at the same time when a ready/busy signal is disabled after generation of the read command; and

storing the latched data bits simultaneously in the cache buffers coupled to the page buffers in response to the cache input control signals.

19. The method as set forth in claim 18, wherein the enabling step comprises:

changing the bit signals of the chip enable signal simultaneously into a predetermined logic value when the read command is generated and maintaining the bit signals at the predetermined logic value while the ready/busy signal is being disabled.

20. The method as set forth in claim 17, wherein the outputting step comprises:

enabling the cache output control signals one by one in sequence for a predetermined time in response to the bit signals of a chip enable signal;

outputting the data bit stored in a corresponding one of the cache buffers, to the external device in response to an enabled one of the cache output control signals; and

repeating the enabling-cache-output-control-signals step and outputting step until the data bit stored in the last one of the cache buffers is output to the external device.

21. The method as set forth in claim 20, wherein the enabling step comprises:

changing the bit signals of the chip enable signal into a predetermined logic value one by one in sequence for the predetermined time after the output data bits are simultaneously stored in the cache buffers.