DIGITALLY CONTROLLED PHASE INTERPOLATOR CIRCUIT

• US 20090238307A1
• Filed: 03/21/2008
• Published: 09/24/2009
• Est. Priority Date: 03/21/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Singh, Ullas
• Granted Patent: US 8,170,150 B2
• Time in Patent Office: Days
• US Class Current: 375/332
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

Digitally controlled phase interpolator circuit. A phase selection control word undergoes decoding to generate a switch control word. The phase selection control word includes 2 quadrant indicating bits and phase interpolating bits for a 4 clock scheme (e.g., 4 clocks having phases 0°, 90°, 180°, and 270°). Such a phase selection control word could includes 3 sector indicating bits and phase interpolating bits for an 8 clock scheme (e.g., 8 clocks having phases 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). The gates of a number of differential pairs of transistors receive the various clock signals. A number of switching circuits direct current from corresponding current sources/supplies to coupled sources of the differential pairs of transistors, and an output clock is taken from coupled drains of the differential pairs of transistors. One or more current sources/supplies can be implemented to provide continuous current (e.g., in an always on manner) to the differential pairs of transistors.

Claims

1. An apparatus, comprising:

a plurality of decoders implemented to receive a phase selection control word that includes 2 quadrant indicating bits and a plurality of phase interpolating bits, wherein;

a first phase decoder of the plurality of decoders processes the 2 quadrant indicating bits and a first phase interpolating bit of the plurality of phase interpolating bits thereby generating a first switch control word; and

a second decoder of the plurality of decoders processes the 2 quadrant indicating bits and a second phase interpolating bit of the plurality of phase interpolating bits thereby generating a second switch control word;

a plurality of differential pairs of transistors, wherein;

gates of each differential pair of the plurality of differential pairs of transistors is implemented to receive one clock signal of a plurality of clock signals; and

sources of each differential pair of the plurality of differential pairs of transistors are coupled together; and

a plurality of switching circuits, wherein;

a first switching circuit of the plurality of switching circuits includes a first plurality of switches such that one end of each switch of the first plurality of switches is coupled to a first current supply; and

a second switching circuit of the plurality of switching circuits includes a second plurality of switches such that one end of each switch of the second plurality of switches is coupled to a second current supply; and

wherein;

the first switch control word controls the first plurality of switches thereby directing current from the first current supply to coupled sources of a first selected differential pair of the plurality of differential pairs of transistors;

the second switch control word controls the second plurality of switches thereby directing current from the second current supply to coupled sources of a second selected differential pair of the plurality of differential pairs of transistors; and

an output signal is output from coupled drains of the plurality of differential pairs of transistors.

2. The apparatus of claim 1, further comprising:

a third current supply that always supplies current to coupled sources of the first selected differential pair of the plurality of differential pairs of transistors; and

a fourth current supply that always supplies current to the coupled sources of second selected phase differential pair of the plurality of differential pairs of transistors.

3. The apparatus of claim 2, wherein:

a third switching circuit of the plurality of switching circuits includes a third plurality of switches such that one end of each switch of the third plurality of switches is coupled to a third current supply; and

further comprising;

a fifth current supply that always supplies current to a third selected differential pair of the plurality of differential pairs of transistors.

4. The apparatus of claim 1, wherein:

the plurality of phase interpolating bits includes N bits such that N is an integer;

the plurality of decoders includes N decoders; and

each decoder of the N decoders receives only one bit of the N bits of the plurality of phase interpolating bits.

5. The apparatus of claim 1, wherein:

the plurality of differential pairs of transistors includes 4 differential pairs of transistors implemented using 8 n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs);

a first differential pair includes a first N-MOSFET and a second N-MOSFET whose sources are coupled together and connect to an end of a first switch of the first plurality of switches that is not coupled to the first current supply; and

a second differential pair includes a third N-MOSFET and a fourth N-MOSFET whose sources are coupled together and connect to an end of a second switch of the first plurality of switches that is not coupled to the first current supply.

6. The apparatus of claim 1, wherein:

the plurality of clock signals includes a first clock signal having a 0 degree phase and a second clock signal having a 90 degree phase;

a third clock signal having a 180 degree phase is generated by switching a polarity of the first clock signal having the 0 degree phase; and

a fourth clock signal having a 270 degree phase is generated by switching a polarity of the second clock signal having the 90 degree phase.

7. The apparatus of claim 1, wherein:

the plurality of clock signals includes a first clock signal having a 0 degree phase, a second clock signal having a 90 degree phase, a third clock signal having a 180 degree phase, and a fourth clock signal having a 270 degree phase;

the plurality of differential pairs of transistors is implemented using n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs);

a first differential pair includes a first N-MOSFET and a second N-MOSFET;

a second differential pair includes a third N-MOSFET and a fourth N-MOSFET;

a third differential pair includes a fifth N-MOSFET and a sixth N-MOSFET;

a fourth differential pair includes a seventh N-MOSFET and an eighth N-MOSFET;

the first clock signal is provided to a gate of the first N-MOSFET and to a gate of the fourth N-MOSFET;

the second clock signal is provided to a gate of the second N-MOSFET and to a gate of the third N-MOSFET;

the third clock signal is provided to a gate of the fifth N-MOSFET and to a gate of the eighth N-MOSFET; and

the fourth clock signal is provided to a gate of the sixth N-MOSFET and to a gate of the seventh N-MOSFET.

8. The apparatus of claim 1, wherein:

each of the first switch control word and the second switch control word includes a same number of bits.

9. The apparatus of claim 1, wherein:

the apparatus is implemented within a serializer/de-serializer.

10. The apparatus of claim 1, wherein:

the apparatus is implemented within a communication device; and

the communication device is implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.

11. An apparatus, comprising:

a plurality of decoders implemented to receive a phase selection control word that includes 2 quadrant indicating bits and a plurality of phase interpolating bits, wherein;

a first phase decoder of the plurality of decoders processes the 2 quadrant indicating bits and a first phase interpolating bit of the plurality of phase interpolating bits thereby generating a first switch control word; and

a second decoder of the plurality of decoders processes the 2 quadrant indicating bits and a second phase interpolating bit of the plurality of phase interpolating bits thereby generating a second switch control word;

a plurality of differential pairs of transistors, wherein;

gates of each differential pair of the plurality of differential pairs of transistors is implemented to receive one clock signal of a plurality of clock signals; and

sources of each differential pair of the plurality of differential pairs of transistors are coupled together; and

a plurality of switching circuits, wherein;

a first switching circuit of the plurality of switching circuits includes a first plurality of switches such that one end of each switch of the first plurality of switches is coupled to a first current supply; and

a second switching circuit of the plurality of switching circuits includes a second plurality of switches such that one end of each switch of the second plurality of switches is coupled to a second current supply;

a third current supply; and

a fourth current supply; and

wherein;

each of the first switch control word and the second switch control word includes a same number of bits;

the first switch control word controls the first plurality of switches thereby directing current from the first current supply to coupled sources of a first selected differential pair of the plurality of differential pairs of transistors;

the second switch control word controls the second plurality of switches thereby directing current from the second current supply to coupled sources of a second selected differential pair of the plurality of differential pairs of transistors;

the third current supply always supplies current to the coupled sources of the first selected differential pair of the plurality of differential pairs of transistors;

the fourth current supply always supplies current to the coupled sources of the second selected phase differential pair of the plurality of differential pairs of transistors; and

an output signal is output from coupled drains of the plurality of differential pairs of transistors.

12. The apparatus of claim 11, wherein:

the plurality of phase interpolating bits includes N bits such that N is an integer;

the plurality of decoders includes N decoders; and

each decoder of the N decoders receives only one bit of the N bits of the plurality of phase interpolating bits.

13. The apparatus of claim 11, wherein:

the plurality of differential pairs of transistors includes 4 differential pairs of transistors implemented using 8 n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs);

a first differential pair includes a first N-MOSFET and a second N-MOSFET whose sources are coupled together and connect to an end of a first switch of the first plurality of switches that is not coupled to the first current supply; and

a second differential pair includes a third N-MOSFET and a fourth N-MOSFET whose sources are coupled together and connect to an end of a second switch of the first plurality of switches that is not coupled to the first current supply.

14. The apparatus of claim 11, wherein:

the plurality of clock signals includes a first clock signal having a 0 degree phase and a second clock signal having a 90 degree phase;

a third clock signal having a 180 degree phase is generated by switching a polarity of the first clock signal having the 0 degree phase; and

a fourth clock signal having a 270 degree phase is generated by switching a polarity of the second clock signal having the 90 degree phase.

15. The apparatus of claim 11, wherein:

the plurality of clock signals includes a first clock signal having a 0 degree phase, a second clock signal having a 90 degree phase, a third clock signal having a 180 degree phase, and a fourth clock signal having a 270 degree phase;

the plurality of differential pairs of transistors is implemented using n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs);

a first differential pair includes a first N-MOSFET and a second N-MOSFET;

a second differential pair includes a third N-MOSFET and a fourth N-MOSFET;

a third differential pair includes a fifth N-MOSFET and a sixth N-MOSFET;

a fourth differential pair includes a seventh N-MOSFET and an eighth N-MOSFET;

the first clock signal is provided to a gate of the first N-MOSFET and to a gate of the fourth N-MOSFET;

the second clock signal is provided to a gate of the second N-MOSFET and to a gate of the third N-MOSFET;

the third clock signal is provided to a gate of the fifth N-MOSFET and to a gate of the eighth N-MOSFET; and

the fourth clock signal is provided to a gate of the sixth N-MOSFET and to a gate of the seventh N-MOSFET.

16. The apparatus of claim 11, wherein:

the apparatus is implemented within a communication device; and

the communication device is implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.

17. An apparatus, comprising:

a plurality of decoders implemented to receive a phase selection control word that includes 2 quadrant indicating bits and a plurality of phase interpolating bits, wherein;

a first phase decoder of the plurality of decoders processes the 2 quadrant indicating bits and a first phase interpolating bit of the plurality of phase interpolating bits thereby generating a first switch control word; and

a second decoder of the plurality of decoders processes the 2 quadrant indicating bits and a second phase interpolating bit of the plurality of phase interpolating bits thereby generating a second switch control word;

a clock processing module implemented to;

process a first clock signal thereby generating a second clock signal; and

process a third clock signal thereby generating a fourth clock signal;

a plurality of differential pairs of transistors, wherein;

gates of a first differential pair of the plurality of differential pairs is implemented to receive the first clock signal and sources of the first differential pair of the plurality of differential pairs are coupled together;

gates of a second differential pair of the plurality of differential pairs is implemented to receive the second clock signal and sources of the second differential pair of the plurality of differential pairs are coupled together;

gates of a third differential pair of the plurality of differential pairs is implemented to receive the third clock signal and sources of the third differential pair of the plurality of differential pairs are coupled together; and

gates of a fourth differential pair of the plurality of differential pairs is implemented to receive the fourth clock signal and sources of the fourth differential pair of the plurality of differential pairs are coupled together; and

a plurality of switching circuits, wherein;

a first switching circuit of the plurality of switching circuits includes a first plurality of switches such that one end of each switch of the first plurality of switches is coupled to a first current supply; and

a second switching circuit of the plurality of switching circuits includes a second plurality of switches such that one end of each switch of the second plurality of switches is coupled to a second current supply;

a third current supply; and

a fourth current supply; and

wherein;

the first switch control word controls the first plurality of switches thereby directing current from the first current supply to coupled sources of the first selected differential pair of the plurality of differential pairs of transistors;

the second switch control word controls the second plurality of switches thereby directing current from the second current supply to coupled sources of the second selected differential pair of the plurality of differential pairs of transistors;

the third current supply always supplies current to the coupled sources of the first selected differential pair of the plurality of differential pairs of transistors; and

the fourth current supply always supplies current to the coupled sources of the second selected phase differential pair of the plurality of differential pairs of transistors; and

an output signal is output from coupled drains of the plurality of differential pairs of transistors.

18. The apparatus of claim 17, wherein:

the plurality of phase interpolating bits includes N bits such that N is an integer;

the plurality of decoders includes N decoders; and

each decoder of the N decoders receives only one bit of the N bits of the plurality of phase interpolating bits.

19. The apparatus of claim 17, wherein:

each of the first switch control word and the second switch control word includes a same number of bits.

20. The apparatus of claim 17, wherein:

the apparatus is implemented within a communication device; and

the communication device is implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.