MEMORY DEVICE WITH MULTIPLE-ACCURACY READ COMMANDS

• US 20090240872A1
• Filed: 03/17/2009
• Published: 09/24/2009
• Est. Priority Date: 03/18/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Perlmutter, Uri, Sokolov, Dotan, Sommer, Naftali, Kasorla, Yoav
• Granted Patent: US 8,059,457 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A method for data storage includes defining at least first and second read commands for reading storage values from analog memory cells. The first read command reads the storage values at a first accuracy, and the second read command reads the storage values at a second accuracy, which is finer than the first accuracy. A condition is evaluated with respect to a read operation that is to be performed over a given group of the memory cells. One of the first and second read commands is selected responsively to the evaluated condition. The storage values are read from the given group of the memory cells using the selected read command.

Claims

1. A method for data storage, comprising:

defining at least first and second read commands for reading storage values from analog memory cells, such that the first read command reads the storage values at a first accuracy and the second read command reads the storage values at a second accuracy, which is finer than the first accuracy;

evaluating a condition with respect to a read operation that is to be performed over a given group of the memory cells;

selecting one of the first and second read commands responsively to the evaluated condition; and

reading the storage values from the given group of the memory cells using the selected read command.

2. The method according to claim 1, wherein the first read command has a first execution time, and wherein the second read command has a second execution time that is longer than the first execution time.

3. The method according to claim 1, wherein reading the storage values comprises sensing the storage values over a first sense time duration when using the first read command, and sensing the storage values over a second sense time duration, which is longer than the first sense time duration, when using the second read command.

4. The method according to claim 1, wherein reading the storage values comprises comparing the read storage values to a first number of read thresholds when using the first read command, and comparing the read storage values to a second number of the read thresholds, which is larger than the first number, when using the second read command.

5. The method according to claim 1, wherein reading the storage values comprises applying to the read storage values a first signal processing process having a first execution time when using the first read command, and applying to the read storage values a second signal processing process having a second execution time, which is longer than the first execution time, when using the second read command.

6. The method according to claim 5, wherein the analog memory cells are comprised in a memory device that is connected to a memory controller, wherein applying the first signal processing process comprises performing the first signal processing process by circuitry comprised in the memory device, and wherein applying the second signal processing process comprises performing the second signal processing process by the memory controller.

7. The method according to claim 6, wherein the first and second signal processing processes comprise interference cancellation processes.

8. The method according to claim 1, wherein reading the storage values comprises comparing the read storage values to one or more read thresholds, adaptively adjusting the read thresholds when using the second read command, and refraining from adaptively adjusting the read thresholds when using the first read command.

9. The method according to claim 1, wherein reading the storage values comprises canceling interference in the read storage values when using the second read command, and refraining from canceling the interference when using the first read command.

10. The method according to claim 1, wherein reading the storage values comprises producing respective hard metrics of the read storage values when using the first read command, and producing respective soft metrics of the read storage values when using the second read command.

11. The method according to claim 1, wherein the storage values in the given group of the memory cells represent stored data, and wherein evaluating the condition and selecting the one of the read commands comprise making an attempt to read the storage values from the memory cells in the group and to reconstruct the stored data, and selecting the one of the first and second read commands responsively to the attempt.

12. The method according to claim 11, wherein the stored data is encoded with an Error Correction Code (ECC), and wherein making the attempt comprises decoding the ECC.

13. The method according to claim 11, wherein making the attempt comprises reading the storage values using the first read command, and, responsively to a failure in reconstructing the stored data, re-attempting to read the storage values and reconstruct the stored data using the second read command.

14. The method according to claim 13, wherein re-attempting to reconstruct the stored data comprises reconstructing the stored data using both the storage values read by the first read command and the re-read storage values read using the second read command.

15. The method according to claim 1, wherein evaluating the condition comprises assessing a wear level of the group of the memory cells.

16. The method according to claim 1, wherein evaluating the condition and selecting the one of the read commands comprise selecting the first read command responsively to determining that the read operation reads the storage values from potentially-interfering memory cells in an interference cancellation process.

17. The method according to claim 1, wherein evaluating the condition and selecting the one of the read commands comprise selecting the first read command responsively to determining that the read operation verifies the storage values that were written into the given group of the memory cells.

18. The method according to claim 1, wherein each of the memory cells in the given group stores at least first and second bits, and wherein evaluating the condition and selecting the one of the read commands comprise selecting the first read command responsively to determining that the read operation reads the first bits from the memory cells, and selecting the second read command responsively to determining that the read operation reads the second bits from the memory cells.

19. The method according to claim 1, wherein evaluating the condition and selecting the one of the read commands comprise selecting the first read command responsively to determining that the read operation is used for estimating a statistical distribution of the storage values that were written into the given group of the memory cells.

20. The method according to claim 1, wherein the read commands have respective attributes, and wherein defining the read commands comprises configuring at least one of the attributes.

21. The method according to claim 20, wherein configuring the at least one attribute comprises estimating an impairment in the analog memory cells, and setting the attribute responsively to estimated impairment.

22. Apparatus for data storage, comprising:

a plurality of analog memory cells; and

circuitry, which is configured to execute at least first and second read commands for reading storage values from the analog memory cells, such that the first read command reads the storage values at a first accuracy and the second read command reads the storage values at a second accuracy that is finer than the first accuracy, and which is operative to evaluate a condition with respect to a read operation that is to be performed over a given group of the memory cells, to select one of the first and second read commands responsively to the evaluated condition, and to read the storage values from the given group of the memory cells using the selected read command.

23. The apparatus according to claim 22, wherein the analog memory cells are arrayed in a memory device, and wherein the circuitry comprises:

first circuitry, which is comprised in the memory device and is coupled to receive the selected one of the first and second read commands over an interface and to read the storage values at a respective one of the first and second accuracies; and

second circuitry, which is separate from the memory device and is coupled to evaluate the condition, to select the one of the first and second read commands and to send the selected command to the first circuitry over the interface for execution.

24. The apparatus according to claim 22, wherein the first read command has a first execution time, and wherein the second read command has a second execution time that is longer than the first execution time.

25. The apparatus according to claim 22, wherein the circuitry is configured to sense the storage values over a first sense time duration when executing the first read command, and to sense the storage values over a second sense time duration that is longer than the first sense time duration when executing the second read command.

26. The apparatus according to claim 22, wherein the circuitry is configured to compare the read storage values to a first number of read thresholds when executing the first read command, and to compare the read storage values to a second number of the read thresholds that is larger than the first number when executing the second read command.

27. The apparatus according to claim 22, wherein the circuitry is configured to apply to the read storage values a first signal processing process having a first execution time when executing the first read command, and to apply to the read storage values a second signal processing process having a second execution time, which is longer than the first execution time, when executing the second read command.

28. The apparatus according to claim 27, wherein the analog memory cells are arrayed in a memory device, and wherein the circuitry comprises:

first circuitry, which is comprised in the memory device and is configured to apply the first signal processing process; and

second circuitry, which is separate from the memory device and is configured to apply the second signal processing process.

29. The apparatus according to claim 28, wherein the first and second signal processing processes comprise interference cancellation processes.

30. The apparatus according to claim 22, wherein the circuitry is configured to compare the read storage values to one or more read thresholds, to adaptively adjust the read thresholds when executing the second read command, and to refrain from adaptively adjusting the read thresholds when executing the first read command.

31. The apparatus according to claim 22, wherein the circuitry is configured to cancel interference in the read storage values when executing the second read command, and to refrain from canceling the interference when executing the first read command.

32. The apparatus according to claim 22, wherein the circuitry is configured to produce respective hard metrics of the read storage values when executing the first read command, and to produce respective soft metrics of the read storage values when executing the second read command.

33. The apparatus according to claim 22, wherein the storage values in the given group of the memory cells represent stored data, and wherein the circuitry is configured to make an attempt to read the storage values from the memory cells in the group and to reconstruct the stored data, and to select the one of the first and second read commands responsively to the attempt.

34. The apparatus according to claim 33, wherein the stored data is encoded with an Error Correction Code (ECC), and wherein the circuitry is configured to reconstruct the stored data by decoding the ECC.

35. The apparatus according to claim 33, wherein the circuitry is configured to read the storage values using the first read command, and, responsively to a failure in reconstructing the stored data, to re-attempt to read the storage values and reconstruct the stored data using the second read command.

36. The apparatus according to claim 33, wherein the circuitry is configured to re-attempt to reconstruct the stored data using both the storage values read by the first read command and the re-read storage values read using the second read command.

37. The apparatus according to claim 22, wherein the circuitry is configured to evaluate the condition by assessing a wear level of the group of the memory cells.

38. The apparatus according to claim 22, wherein the circuitry is configured to select the first read command responsively to determining that the read operation reads the storage values from potentially-interfering memory cells in an interference cancellation process.

39. The apparatus according to claim 22, wherein the circuitry is configured to select the first read command responsively to determining that the read operation verifies the storage values that were written into the given group of the memory cells.

40. The apparatus according to claim 22, wherein each of the memory cells in the given group stores at least first and second bits, and wherein the circuitry is configured to select the first read command responsively to determining that the read operation reads the first bits from the memory cells, and to select the second read command responsively to determining that the read operation reads the second bits from the memory cells.

41. The apparatus according to claim 22, wherein the circuitry is configured to select the first read command responsively to determining that the read operation is used for estimating a statistical distribution of the storage values that were written into the given group of the memory cells.

42. The apparatus according to claim 22, wherein the read commands have respective attributes, and wherein the circuitry is configured to configure at least one of the attributes.

43. The apparatus according to claim 42, wherein the circuitry is configured to estimate an impairment in the analog memory cells, and to set the attribute responsively to estimated impairment.

44. Apparatus for data storage, comprising:

a plurality of analog memory cells; and

circuitry, which is coupled to receive a given read command for reading respective storage values from a given group of the analog memory cells, wherein the given read command is selected from at least a first read command that reads the storage values at a first accuracy and a second read command that reads the storage values at a second accuracy that is finer than the first accuracy, and to read the storage values from the given group of the memory cells at one of the first and second accuracies corresponding to the given read command.