Multi-Level Striping and Truncation Channel-Equalization for Flash-Memory System
First Claim
1. A two-level flash device comprising:
- a smart storage switch which comprises;
an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;
a smart storage transaction manager that manages transactions from the host;
a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping;
a high-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity and a scattered capacity for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels;
a virtual storage bridge between the smart storage transaction manager and a NVM controller through a LBA bus;
a plurality of NVM controllers, each NVM controller coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge;
a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped;
a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises;
NVM flash memory, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the low-level mapper in the NVM controller, and at a page location identified by the page number for the page-mapped host data.
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Accused Products
Abstract
Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers.
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Citations
22 Claims
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1. A two-level flash device comprising:
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a smart storage switch which comprises; an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping; a high-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity and a scattered capacity for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels; a virtual storage bridge between the smart storage transaction manager and a NVM controller through a LBA bus; a plurality of NVM controllers, each NVM controller coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped; a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises; NVM flash memory, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the low-level mapper in the NVM controller, and at a page location identified by the page number for the page-mapped host data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A three-level flash device comprising:
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a high-level smart storage switch which comprises; an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping; a high-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity and a scattered capacity for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels; a virtual storage bridge between the smart storage transaction manager and a LBA bus; a second-level smart storage switch which comprises; a second upstream interface to the high-level smart storage switch for receiving commands to access NVM and for receiving data and an address from the high-level smart storage switch; a second-level smart storage transaction manager that manages transactions from NVM devices; a channel storage processor that maps the address from the high-level smart storage switch to an assigned flash channel to generate a local logical block address (LBA), the channel storage processor performing a mapping to multiple NVM devices attached to the second-level smart storage switch; a second-level mapper, coupled to the channel storage processor, that stores a physical capacity and swap capacity of all NVM devices for each flash channel, wherein the physical capacity for all NVM devices has a different value of bad blocks, wherein the swap capacity varies among the flash channels; a plurality of NVM controllers, each NVM controller coupled to the LBA bus to receive the LBA generated by the channel storage processor and the data from the second-level smart storage switch; a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped; a plurality of flash channels that include the assigned flash channel, wherein a flash channel comprises; NVM flash memory, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the low-level mapper in the NVM controller, and at a page location identified by the page number for the page-mapped host data; wherein the second-level smart storage switch accesses the plurality of flash channels as a stripe of multiple simultaneous accesses of the plurality of flash channel for data stored in the stripe capacity; wherein the second-level smart storage switch accesses the plurality of flash channels as a single-channel access of one flash channel at a time for data stored in the scattered capacity; whereby the scattered data is accessed as single-channel access while the striped data is accessed using multiple simultaneous accesses. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A smart storage switch two-level controller comprising:
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a smart storage switch which comprises; an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping; a first-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity and a scattered capacity for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels; a virtual storage bridge between the smart storage transaction manager and a NVM controller through a LBA bus; a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; and a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped.
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20. A smart storage switch comprising:
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an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping; a first-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity and a scattered capacity for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels; a virtual storage bridge between the smart storage transaction manager and a NVM controller through a LBA bus.
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21. A smart storage switch three-level controller comprising:
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a first-level smart storage switch which comprises; an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping; a first-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity and a scattered capacity for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels; a virtual storage bridge between the smart storage transaction manager and a LBA bus; a second-level smart storage switch which comprises; a second upstream interface to the first-level smart storage switch for receiving commands to access NVM and for receiving data and an address from the first-level smart storage switch; a second-level smart storage transaction manager that manages transactions from the NVM devices; a second-level stripping mapper, coupled to the channel storage processor, that stores a physical capacity and swap capacity of all NVM devices for each flash channel, wherein the physical capacity for all NVM devices has a different value of bad blocks, wherein the swap capacity varies among the flash channels; a channel storage processor that maps the address from the first-level smart storage switch to an assigned flash channel to generate a local logical block address (LBA), the channel storage processor performing a mapping to multiple NVM devices attached to the second-level smart storage switch; a NVM controller, coupled to the LBA bus to receive the LBA generated by the channel storage processor and the data from the second-level smart storage switch; and a low-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA), the low-level mapper generating the PBA for block-mapped host data, and the low-level mapper generating the PBA and a page number for host data that is page-mapped.
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22. A smart storage switch three-level controller comprising:
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a first-level smart storage switch which comprises; an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address; a smart storage transaction manager that manages transactions from the host; a virtual storage processor that maps the host address to an assigned flash channel to generate a logical block address (LBA), the virtual storage processor performing a high level of mapping; a first-level striping mapper, coupled to the virtual storage processor, that stores a stripe capacity and a scattered capacity for each flash channel, wherein the stripe capacity for all flash channels has a same value, wherein the scattered capacity varies among the flash channels; a virtual storage bridge between the smart storage transaction manager and a LBA bus; a second-level smart storage switch which comprises; a second upstream interface to the first-level smart storage switch for receiving commands to access NVM and for receiving data and an address from the first-level smart storage switch; a second-level smart storage transaction manager that manages transactions from the NVM devices; a second-level stripping mapper, coupled to the channel storage processor, that stores a physical capacity and swap capacity of all NVM devices for each flash channel, wherein the physical capacity for all NVM devices has a different value of bad blocks, wherein the swap capacity varies among the flash channels; a channel storage processor that maps the address from the first-level smart storage switch to an assigned flash channel to generate a local logical block address (LBA), the channel storage processor performing a mapping to multiple NVM devices attached to the second-level smart storage switch.
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Specification