Circuitized substrate and method of making same

• US 20090241332A1
• Filed: 03/28/2008
• Published: 10/01/2009
• Est. Priority Date: 03/28/2008
• Status: Abandoned Application

• Current Assignee: I3 ELECTRONICS, INC.
• Original Assignee: I3 ELECTRONICS, INC.
• Inventors: Paoletti, James P., Rai, Rajinder S., Lauffer, John M., Markovich, Voya R., Papathomas, Kostas I., Magnuson, Roy H.
• Application Number:
  US12/078,206
• Publication Number:
  US 20090241332A1
• Time in Patent Office: Days
• US Class Current: 29/829
• CPC Class Codes: H05K 2201/09318 Core having one signal plane and one power plane
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2203/061 of previously made multilayered subassemblies
• CPC Class Codes: H05K 3/0032 of organic insulating material
• CPC Class Codes: H05K 3/4069 for via connections in organic insulating substrates
• CPC Class Codes: H05K 3/462 characterized by laminating only or mainly similar double-sided circuit boards
• CPC Class Codes: H05K 3/4623 the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.

Abstract

A circuitized substrate and method of making same in which a first plurality of holes are formed within two bonded dielectric layers and then made conductive, e.g., plated. The substrate also includes third and fourth dielectric layers bonded to the first and second with a plurality of continuous electrically conductive thru holes extending through all four dielectric layers. Conductive paste is positioned within the thru holes for providing electrical connections between desired conductive layers of the substrate and outer layers as well. A circuitized substrate assembly and method of making same are also provided.

Claims

1. A method of making a circuitized substrate comprising:

providing a first conductive circuit layer having first and second sides;

bonding a first dielectric layer having a first thickness to said first side of said conductive circuit layer and a second dielectric layer having a second thickness to said second side of said conductive circuit layer;

forming a first plurality of holes within said first and second dielectric layers, said first plurality of holes extending through said first and second dielectric layers;

bonding third and fourth dielectric layers to said first and second dielectric layers, respectively, such that said first and third dielectric layers will have a combined third thickness and that said second and fourth dielectric layers will have a combined fourth thickness;

forming a second plurality of holes within each of said first, second, third and fourth dielectric layers, each of said second plurality of holes being in alignment with a respective one of said first plurality of holes within said first and second dielectric layers to thereby form a plurality of continuous holes through said first, second, third and fourth dielectric layers; and

positioning a quantity of conductive paste within each of said continuous holes to thereby form a plurality of continuous thru-holes each having a length such that said conductive paste within each of said thru-holes will possess a relatively low resistivity.

2. The method of claim 1 further including forming a conductive layer on each of said first plurality of holes within said first and second dielectric layers prior to said bonding of said third and fourth dielectric layers to said first and second dielectric layers, respectively.

3. The method of claim 2 wherein said forming of said conductive layer on said first plurality of holes is accomplished using an electroplating operation.

4. The method of claim 1 wherein said forming of said conductive circuit on said first dielectric layer is accomplished using photolithographic processing.

5. The method of claim 4 wherein said first conductive circuit is formed as a power plane.

6. The method of claim 1 wherein said bonding of said third and fourth dielectric layers to said first and second dielectric layers, respectively, is accomplished while said third and fourth dielectric layers are in a partially cured state.

7. The method of claim 1 wherein said positioning of said quantity of conductive paste within each of said continuous holes is accomplished using a step selected from the group of steps consisting of stencil printing, screen printing, doctor blade or injection deposition.

8. The method of claim 1 wherein said forming of said first plurality of holes within said first and second dielectric layers and extending through said first and second dielectric layers is accomplished using laser or mechanical drilling.

9. The method of claim 1 wherein said forming of said second plurality of holes within said first, second, third and fourth dielectric layers in alignment with a respective one of said first plurality of holes within said first and second dielectric layers to thereby form a plurality of continuous holes through said first, second, third and fourth dielectric layers is accomplished using laser or mechanical drilling.

10. The method of claim 1 further including bonding said circuitized substrate to at least one other circuitized substrate to form a circuitized substrate assembly.

11. The method of claim 10 wherein said bonding of said circuitized substrate to said at least one other circuitized substrate to form a circuitized substrate assembly is accomplished using a lamination process.

12. The method of claim 10 further including electrically coupling at least one electrical component to said circuitized substrate assembly.

13. A circuitized substrate comprising:

a first dielectric layer having a first thickness;

a conductive circuit positioned on said first dielectric layer;

a second dielectric layer having a second thickness bonded to said conductive circuit;

a first plurality of holes extending through said first and second dielectric layers and including an electrically conductive layer thereon;

third and fourth dielectric layers bonded to said first and second dielectric layers, respectively;

a plurality of continuous thru holes extending through said first, second third and fourth dielectric layers, each of said plurality of continuous thru holes being in alignment with a respective one of said first plurality of holes within said first and second dielectric layers and including a quantity of electrically conductive paste therein, said electrically conductive paste possessing a relatively low resistivity.

14. The circuitized substrate of claim 13 wherein said first and second dielectric layers are each comprised of a low dielectric constant, low dielectric loss material.

15. The circuitized substrate of claim 13 wherein said conductive circuit on said first dielectric layer comprises a power plane.

16. The circuitized substrate of claim 13 wherein said electrically conductive layer on said first plurality of holes is comprised of copper or copper alloy.

17. The circuitized substrate of claim 13 wherein said third and fourth dielectric layers bonded to said first and second dielectric layers are each comprised of a low dielectric constant, low dielectric loss material.

18. The circuitized substrate of claim 13 further including a second circuitized substrate bonded thereto, said circuitized substrate and said second circuitized substrate forming a circuitized substrate assembly.

19. The invention of claim 18 further including at least one electrical component electrically coupled to said circuitized substrate assembly.

20. The invention of claim 19 wherein said at least one electrical component comprises a semiconductor chip.