THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY

• US 20090242889A1
• Filed: 09/13/2007
• Published: 10/01/2009
• Est. Priority Date: 10/02/2006
• Status: Abandoned Application

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Nakayama, Tetsuo
• Application Number:
  US12/442,460
• Publication Number:
  US 20090242889A1
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

Disclosed is a thin film transistor which is characterized by including a gate electrode 3, a gate insulating film 4, a channel layer 5 and source/drain layers 7, 8 stacked over a substrate 2 in this order or in reverse order, wherein the source/drain layers 7, 8 include n-type microcrystalline silicon layers 7a, 8a and n-type amorphous silicon layers 7b, 8b, which are so arranged that the n-type microcrystalline silicon layers 7a, 8a are on the channel layer 5 side. Also disclosed are a method for manufacturing such a thin film transistor and a display.

Claims

1. A thin film transistor is characterized by comprising a gate electrode, a gate insulating film, a channel layer, and source/drain layers stacked over a substrate in this order or in reverse order,

wherein said source/drain layers each include a microcrystalline silicon layer and an amorphous silicon layer, which are so arranged that said microcrystalline silicon layer is on the channel layer side.

2. The thin film transistor according to claim 1,

wherein said thin film transistor is characterized that it is of n-channel type.

3. A method for manufacturing a thin film transistor, is characterized by comprising:

a step of forming a gate insulating film over a substrate, with a gate electrode therebetween;

a step of forming a channel layer over said gate insulating layer; and

a step of forming source/drain layers each including a microcrystalline silicon layer and an amorphous silicon layer sequentially stacked over said channel layer.

4. A method for manufacturing a thin film transistor, is characterized by comprising:

a step of forming source/drain layers each including an amorphous silicon layer and a microcrystalline silicon layer sequentially stacked over a substrate;

a step of forming a channel layer over said source/drain layers; and

a step of forming a gate electrode over said channel layer, with a gate insulating film therebetween.

5. A display is characterized by comprising a substrate over which thin film transistors and display elements connected to said thin film transistors are formed in an arrayed manner, each of said thin film transistors including a gate electrode, a gate insulating film, a channel layer, and source/drain layers stacked over said substrate in this order or in reverse order, wherein said source/drain layers each include a microcrystalline silicon layer and an amorphous silicon layer, which are so arranged that said microcrystalline layer is on the channel layer side.