SHALLOW TRENCH CAPACITOR COMPATIBLE WITH HIGH-K / METAL GATE

• US 20090242953A1
• Filed: 03/31/2008
• Published: 10/01/2009
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Booth, Roger A. JR., Brodsky, MaryJane, Cheng, Kangguo, Pei, Chengwen
• Granted Patent: US 7,875,919 B2
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors

Abstract

Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

Claims

1. A shallow trench capacitor comprising:

an STI trench extending into a surface of a substrate and having a depth (d) and a width (w), wherein the depth (d) of the STI trench is less than 5 times the width (w) of the STI trench;

a cell well implanted to have a first polarity encompassing the STI trench;

the STI trench is filled with a gate stack comprising an insulating layer followed by a conductive layer;

the gate stack is patterned so as to have a portion located over the STI trench; and

source/drain implantations in the substrate on opposite sides of the STI trench and having the same polarity as the cell well.

2. The shallow trench capacitor of claim 1, wherein:

the STI trench has a depth (d) of approximately 200-300 nm, and a width (w) of at least 100 nm.

3. The shallow trench capacitor of claim 1, further comprising:

an additional implant of the first polarity to increase the doping level in the cell well in adjacent the STI trench.

4. The shallow trench capacitor of claim 1, wherein:

the insulating layer comprises a high-k dielectric material.

5. The shallow trench capacitor of claim 1, wherein:

the conductive layer comprises a metal layer and poly layer overlying the metal layer.

6. A method of forming a shallow trench capacitor in conjunction with an FET comprising:

forming a plurality of STI trenches;

for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches;

for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches;

forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over the third trench; and

performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well.

7. The method of claim 6, wherein:

the second polarity is opposite from the first polarity.

8. The method of claim 6, further comprising:

an additional implant to reduce ESR in the second cell well.

9. A method of forming a capacitor in an integrated circuit chip comprising:

form shallow trench isolations (STIs) comprising shallow trenches filled with a dielectric material;

implant at least one cell well, a portion of which is a cap well and another portion of which is a FET well;

remove the dielectric material from a given one of the shallow trenches in the cap well; and

deposit a gate stack comprising;

a layer of insulating material; and

a layer of a conductive material;

wherein the insulating material lines the given one of the shallow trenches in the cap well, and the metal at least partially fills the given one of the shallow trenches in the cap well;

patterning the gate stack to have two portions, a first portion over the FET well which will serve as a gate stack for a FET, and a second portion which will serve as a contact to an inner electrode of a capacitor which is formed in the given one of the shallow trenches; and

performing source/drain implantation to form a FET comprising source/drain implants and the gate stack for the FET, and to form a buried electrode for the capacitor.

10. The method of claim 9, further comprising:

performing an ion implantation to lower resistance in the cap well.

11. The method of claim 9, wherein:

the insulating material comprises a high-k dielectric material.

12. The method of claim 9, wherein:

the conductive material comprises a metal layer followed by a cap layer of polysilicon.

13. The method of claim 9, further comprising:

forming sidewall spacers on at least the gate stack for the FET.

14. The method of claim 9, wherein:

the cap well is of opposite polarity from the FET well.

15. The method of claim 14, wherein:

the source/drain implantation is the same for the cap well as for the FET well;

thereby there is no channel between the source/drain implantation in the cap well.

16. The method of claim 14, wherein:

the cap well is an n-well;

the FET well is a p-well; and

the source/drain implantation is n-type (n+).

17. A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising:

an STI trench extending into a surface of a substrate and having a depth (d) and a width (w), wherein the depth (d) of the STI trench is less than 5 times the width (w) of the STI trench;

a cell well implanted to have a first polarity encompassing the STI trench;

the STI trench is filled with a gate stack comprising an insulating layer followed by a conductive layer;

the gate stack is patterned so as to have a portion located over the STI trench; and

source/drain implantations in the substrate on opposite sides of the STI trench and having the same polarity as the cell well.

18. The design structure of claim 17 wherein the design structure comprises a netlist, which describes the design.

19. The design structure of claim 17 wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

20. The design structure of claim 17 wherein the design structure includes at least one of test data files, characterization data, verification data, or design specific.