Flash Memory Cell

• US 20090242959A1
• Filed: 03/23/2009
• Published: 10/01/2009
• Est. Priority Date: 03/28/2008
• Status: Active Grant

• Current Assignee: National Tsing Hua University
• Original Assignee: National Tsing Hua University
• Inventors: King, Ya-Chin, Lin, Chrong-Jung
• Granted Patent: US 8,093,649 B2
• Time in Patent Office: Days
• US Class Current: 257/319
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

A flash memory cell is disclosed in the specification and drawing. The flash memory cell is described and shown with at least one floating gate heavily doped with P-type ions.

Claims

1. A flash memory cell, comprising:

a substrate;

a source and a drain formed in the substrate separately, wherein the source and the drain are heavily doped with N-type ions;

a first oxide formed on the substrate;

a floating gate formed on the first oxide, wherein the floating gate is heavily doped with P-type ions;

a second oxide formed on the floating gate; and

a control gate formed on the second oxide.

2. The flash memory cell as claimed in claim 1, wherein the control gate is heavily doped with N-type ions.

3. The flash memory cell as claimed in claim 1, further comprising:

a channel region in the substrate disposed between the source and the drain.

4. The flash memory cell as claimed in claim 1, wherein the floating gate has a curved top surface and at least one sidewall intersecting the curved top surface to form a sharp edge, and the second oxide covers the sharp edge and the sidewall.

5. A flash memory cell, comprising:

a substrate;

a source and a drain formed in the substrate separately, wherein the source and the drain are heavily doped with N-type ions;

a floating gate is disposed above the substrate, wherein the floating gate is heavily doped with P-type ions;

a control gate stacked above the floating gate; and

a select gate positioned to the side of both the floating gate and the control gate.

6. The flash memory cell as claimed in claim 5, wherein the select gate is heavily doped with N-type ions.

7. The flash memory cell as claimed in claim 5, further comprising:

a first oxide on the substrate surrounding the floating gate and extending under the select gate.

8. The flash memory cell as claimed in claim 7, further comprising:

a second oxide on the floating gate surrounding the control gate.

9. A flash memory cell, comprising:

a substrate;

a N-type source and at least two N-type drains formed in the substrate separately, wherein the source is disposed between the drains;

at least two floating gates disposed on opposite sides of the source respectively;

at least two control gates disposed on the floating gates respectively and on opposite sides of the source, wherein the floating gate is heavily doped with P-type ions;

an erase gate disposed directly above the source and between the control gates; and

at least two select gates formed on the sides of both the control gates and the floating gates opposite the erase gate.

10. The flash memory cell as claimed in claim 9, wherein the select gates are heavily doped with N-type ions.