NON-VOLATILE MEMORY DEVICE

• US 20090242964A1
• Filed: 04/19/2007
• Published: 10/01/2009
• Est. Priority Date: 04/26/2006
• Status: Active Grant

• Current Assignee: III Holdings 6, LLC
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Agarwal, Prabhat, Akil, Nader, Van Schaijk, Robertus T.F.
• Granted Patent: US 8,159,018 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least ¾ of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.

Claims

1. A finFET-based non-volatile memory device on a semiconductor substrate comprising source and drain regions, a fin body, a charge trapping stack and a gate;

the fin body extending between the source region and the drain region, the fin connecting the source region and the drain region;

the charge trapping stack being arranged to cover at least a portion of the fin body;

the gate being arranged to cover the charge trapping stack at the location of the fin body, and the fin body having a corner-free shape.

2. A finFET-based non-volatile memory device according to claim 1, wherein the corner-free shape of the fin body is a rounded shape.

3. A finFET-based non-volatile memory device according to claim 1, wherein the fin body has at least a circular shape of an elliptical shape.

4. A finFET-based non-volatile memory device according to claim 1, wherein the fin body is arranged on a silicon dioxide layer, and a surface of the silicon dioxide layer adjacent to the fin body is recessed to a recess level.

5. A finFET-based non-volatile memory device according to claim 4, wherein the recess level is either equal to, or larger than, the thickness of the charge trapping layer and the top insulator layer.

6. A finFET-based non-volatile memory device according to claim 1, wherein the fin body is free-standing.

15. Memory array comprising at least one finFET-based non-volatile memory device in accordance with claim 1.

16. Semiconductor device comprising at least one finFET-based non-volatile memory device in accordance with claim 1.

7. A method for manufacturing a finFET-based non-volatile memory device on a semiconductor substrate comprising source and drain regions, a fin body, a charge trapping stack and a gate;

the fin body extending between the source region and the drain region, the fin connecting the source region and the drain region;

the charge trapping stack being arranged to cover at least a portion of the fin body;

the gate being arranged to cover the charge trapping stack at the location of the fin body, the method comprising;

shaping the fin body in such a way that the fin body has a corner-free shape.

8. A method for manufacturing a finFET-based non-volatile memory device according to claim 7, wherein the shaping of the fin body comprises annealing in hydrogen ambient at an elevated temperature between about 850 and about 1000°

C.

9. A method for manufacturing a finFET-based non-volatile memory device according to claim 7, wherein the substrate (SOI) comprises an insulating layer, which is covered by a monocrystalline silicon layer;

the source and drain regions and the fin body being arranged in the monocrystalline silicon layer, the insulating layer adjacent to the source and drain regions and the fin body being recessed to a recess level.

10. A method for manufacturing a finFET-based non-volatile memory device according to claim 9, wherein the method comprises an etching to provide a recess level that is either equal to, or larger than, the thickness of the charge trapping layer and the top insulator layer.

11. A method for manufacturing a finFET-based non-volatile memory device according to claim 10, wherein the etching is extended to a level that the insulating layer under the fin body is completely removed.

12. A method for manufacturing a finFET-based non-volatile memory device according to claim 11, wherein the etching is achieved by combining a first anisotropic dry etching for partly recessing the insulating layer under the fin body with a second isotropic oxide etching for removing the insulating layer below the fin body.

13. A method for manufacturing a finFET-based non-volatile memory device according to claim 7, wherein the method comprises:

providing a gap region between a surface of the substrate and the fin body in such a way that the fin body is free-standing.

14. A method for manufacturing a finFET-based non-volatile memory device according to claim 13, wherein the substrate comprises a monocrystalline silicon wafer which is covered by an epitaxial Si—

Ge layer, the SiGe layer being covered by an epitaxial Si layer;

the source and drain regions and the fin body being arranged in the epitaxial Si layer and wherein the provision of the gap regions comprises the removal of the epitaxial SiGe layer below the fin body.