SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME

• US 20090242990A1
• Filed: 03/11/2009
• Published: 10/01/2009
• Est. Priority Date: 03/28/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SAITOH, Masumi, UCHIDA, Ken
• Granted Patent: US 8,076,231 B2
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate'"'"'s principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a semiconductor layer having rectangular solid-shape formed at an upper part of the semiconductor substrate to have a top surface being parallel to a principal plane of the semiconductor substrate and a side face with a (100) plane perpendicular to the principal plane of the semiconductor substrate; and

a pMISFET, wherein

the pMISFET has a channel region formed at least at the side face of the semiconductor layer, a gate dielectric film formed at least on the side face of the semiconductor layer, a gate electrode covering the channel region with the gate dielectric film being sandwiched therebetween, and source/drain regions formed within the rectangular solid-shaped semiconductor layer in such a way as to interpose the channel region therebetween, and wherein the channel region is applied a compressive strain in a direction perpendicular to the principal plane of the semiconductor substrate.

2. The device according to claim 1, further comprising:

a second semiconductor layer having rectangular solid-shape formed at the upper part of the semiconductor substrate to have a second top surface being parallel to the principal plane of the semiconductor substrate and a second side surface with a (100) plane perpendicular to the principal plane of the semiconductor substrate; and

an nMISFET, wherein

the nMISFET has a second channel region formed at least at the second side face of the second semiconductor layer, a second gate dielectric film formed at least on the second side face of the second semiconductor layer, a second gate electrode covering the second channel region with the second gate dielectric film being sandwiched therebetween, and second source/drain regions formed within the second semiconductor layer in such a way as to interpose the second channel region therebetween, and wherein the second channel region is applied a compressive strain in a direction perpendicular to the principal plane of the semiconductor substrate whereas the second side face is applied a compressive strain in a direction perpendicular to the second side face.

4. The device according to claim 1, wherein the gate electrode has a multilayer structure of metal and semiconductor films and wherein the semiconductor film has an impurity concentration which becomes higher in a direction of from the semiconductor substrate side of the semiconductor layer to an upside thereof.

5. The device according to claim 1, wherein the gate electrode has a multilayer structure of metal and semiconductor films and wherein the semiconductor film has its lowermost surface which is above the top surface of the semiconductor layer.

6. The device according to claim 1, wherein the gate dielectric film is formed only on the side face of the semiconductor layer.

7. The device according to claim 1, wherein the gate dielectric film is also formed on the top surface of the semiconductor layer.

8. The device according to claim 1, wherein the semiconductor substrate is a SOI substrate.

9. The device according to claim 1, wherein the semiconductor substrate is a bulk silicon substrate.

10. The device according to claim 1, wherein the gate electrode has a multilayer structure of metal and semiconductor films, wherein the semiconductor film has an impurity concentration which becomes higher in a direction of from the semiconductor substrate side of the semiconductor film to an upside thereof, wherein the gate dielectric film is formed only on the side face of the semiconductor layer, and wherein the semiconductor substrate is a SOI substrate.

11. The device according to claim 1, wherein the channel region is applied a tensile strain in a direction perpendicular to the side face.

12. The device according to claim 4, wherein the impurity concentration of the semiconductor film of the gate electrode is greater than or equal to 2×

10¹⁹ per cubic centimeter (cm<sup>−

3</sup>) and less than 2×

10²⁰ cm<sup>−

3</sup> at a lowermost layer on the semiconductor substrate side of the semiconductor film and is more than or equal to 2×

10²¹ cm<sup>−

3</sup> and less than or equal to 2×

10²¹ cm<sup>−

3</sup> at an uppermost layer.

3. A semiconductor device comprising:

a semiconductor substrate;

a first semiconductor layer having rectangular solid-shape formed at an upper part of the semiconductor substrate to have a first top surface being parallel to a principal plane of the semiconductor substrate and a first side face with a (110) plane perpendicular to the principal plane of the semiconductor substrate;

a second semiconductor layer having rectangular solid-shape formed at the upper part of the semiconductor substrate to have a second top surface being parallel to the principal plane of the semiconductor substrate and a second side surface with a (110) plane perpendicular to the principal plane of the semiconductor substrate;

a pMISFET; and

an nMISFET, wherein

the pMISFET has a first channel region formed at least at the first side face of the first semiconductor layer, a first gate dielectric film formed at least on the first side face of the first semiconductor layer, a first gate electrode covering the first channel region with the first gate dielectric film being sandwiched therebetween, and first source/drain regions formed within the first semiconductor layer in such a way as to interpose the first channel region therebetween,

the nMISFET has a second channel region formed at least at the second side face of the second semiconductor layer, a second gate dielectric film formed at least on the second side face of the second semiconductor layer, a second gate electrode covering the second channel region with the second gate dielectric film being sandwiched therebetween, and second source/drain regions formed within the second semiconductor layer in such a way as to interpose the second channel region therebetween, and

the second channel region is applied a compressive strain in a direction perpendicular to the principal plane of the semiconductor substrate.

13. The device according to claim 3, wherein the second channel region is applied a tensile strain in a direction perpendicular to the second side face.

14. A method of manufacturing a semiconductor device, comprising:

forming a plurality of semiconductor layers having rectangular solid-shape at an upper part of a semiconductor substrate;

forming a gate dielectric film at least on side faces of the semiconductor layers;

forming a metal film on the gate dielectric film;

depositing on the metal film a semiconductor film in such a way as to fill a portion between adjacent ones of the semiconductor layers;

performing impurity ion implantation to amorphasize an upper part of the semiconductor film;

patterning the semiconductor film and the metal film to thereby form at least one gate electrode;

forming a stress liner dielectric film on the gate electrode;

performing thermal processing for crystallizing the upper part of the semiconductor film; and

removing the stress liner dielectric film.

15. A method of manufacturing a semiconductor device, comprising:

forming a plurality of semiconductor layers having rectangular solid-shape at an upper part of a semiconductor substrate;

forming a gate dielectric film at least at side faces of the semiconductor layers;

forming a metal film on the gate dielectric film in such a way as to fill a portion between adjacent ones of the semiconductor layers;

planarizing the metal film by polishing;

depositing a semiconductor film on the metal film;

performing impurity ion implantation to amorphasize an upper part of the semiconductor film;

patterning the semiconductor film and the metal film to thereby form at least one gate electrode;

forming a stress liner dielectric film on the gate electrode;

performing thermal processing for crystallizing the upper part of the semiconductor film; and

removing the stress liner dielectric film.