SOI TRANSISTOR WITH FLOATING BODY FOR INFORMATION STORAGE HAVING ASYMMETRIC DRAIN/SOURCE REGIONS

• US 20090242996A1
• Filed: 01/14/2009
• Published: 10/01/2009
• Est. Priority Date: 03/31/2008
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: van Bentum, Ralf, Mohapatra, Nihar-Ranjan
• Application Number:
  US12/353,431
• Publication Number:
  US 20090242996A1
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

By laterally asymmetrically defining the well dopant concentration in a floating body storage transistor, an increased well dopant concentration may be provided at the drain side, while a moderately low concentration may remain in the rest of the floating body region. Consequently, compared to conventional symmetric designs, a reduction in the read/write voltages for switching on the parasitic bipolar transistor may be accomplished, while the increased punch-through immunity may allow further scaling of the gate length of the floating body storage transistor.

Claims

1. A floating body storage transistor, comprising:

a gate electrode formed above a semiconductor region and separated therefrom by a gate insulation layer;

a drain region and a source region formed in said semiconductor region, said drain region and source region defined by a dopant species of a first conductivity type; and

a floating body region located in said semiconductor region adjacent to and in contact with said drain region and said source region so as to form a first PN junction with said drain region and a second PN junction with said source region, said floating body region being defined by a dopant species of a second conductivity type that is opposite to said first conductivity type, a concentration of said dopant species of the second conductivity type being higher at said first PN junction as compared to said second PN junction.

2. The floating body storage transistor of claim 1, wherein a dopant gradient of said first PN junction is steeper compared to a dopant gradient of said second PN junction.

3. The floating body storage transistor of claim 1, wherein a degree of counter-doping caused by said dopant species of said first conductivity type in said source region at a specified depth increases from said gate electrode towards an interface formed by an isolation structure and said source region.

4. The floating body storage transistor of claim 1, wherein a degree of counter-doping caused by said dopant species of said first conductivity type in said source region at a specified depth is substantially constant along a direction from said gate electrode towards an interface formed by an isolation structure and said source region.

5. The floating body storage transistor of claim 1, further comprising a buried insulating layer formed below and in contact with said semiconductor region.

6. The floating body storage transistor of claim 1, further comprising an isolated well region embedded in said semiconductor region, wherein said isolated well region is defined by a dopant species of said second conductivity type.

7. The floating body storage transistor of claim 1, wherein said first conductivity type is an N-type conductivity.

8. The floating body storage transistor of claim 1, wherein said first conductivity type is a P-type conductivity.

9. A semiconductor device, comprising:

a plurality of floating body storage transistors configured to store information on the basis of charge storage in a floating body region, each of said plurality of floating body storage transistors having a well region with an increased well dopant concentration at a PN junction at a drain side compared to a PN junction at a source side.

10. The semiconductor device of claim 9, wherein each of said plurality of floating body storage transistors is a part of a respective one of a memory cell of a memory area of said semiconductor device.

11. The semiconductor device of claim 10, further comprising a CPU core operatively connected to said memory area.

12. The semiconductor device of claim 11, further comprising a static RAM area operatively connected to said CPU core and said memory area.

13. The semiconductor device of claim 9, further comprising a buried insulating layer formed below and in contact with each of said well regions to define an SOI configuration.

14. The semiconductor device of claim 9, wherein each of said well regions is provided as an isolated well region embedded in a semiconductor material.

15. A method of forming a storage transistor, the method comprising:

defining a well region in a semiconductor region in a laterally asymmetric manner with respect to a drain region and a source region to be formed in said well region; and

forming said drain region and said source region by introducing a dopant species of a first conductivity type to define a first PN junction connecting to said drain region and a second PN junction connecting to said source region.

16. The method of claim 15, wherein defining said well region comprises laterally asymmetrically introducing a dopant species of a second conductivity type opposite to said first conductivity type into a semiconductor region to obtain a higher concentration at said first PN junction relative to said second PN junction.

17. The method of claim 16, wherein laterally asymmetrically introducing the dopant species of said second conductivity type comprises forming a gate electrode structure above said semiconductor region and performing at least one implantation process with a tilt angle and using said gate electrode as an implantation mask.

18. The method of claim 16, wherein laterally asymmetrically introducing the dopant species of said second conductivity type comprises masking said source region and performing an implantation process to introduce the dopant species of said second conductivity type.

19. The method of claim 18, further comprising forming a gate electrode structure above said semiconductor region prior to performing said implantation process.

20. The method of claim 18, further comprising forming a gate electrode structure above said semiconductor region after performing said implantation process.

21. The method of claim 15, wherein forming said drain region and said source region comprises introducing a first concentration of a dopant species of said first conductivity type, forming a spacer element on sidewalls of a gate electrode structure and introducing a second concentration of a dopant species of said first conductivity type, wherein said second concentration is higher than said first concentration.

22. The method of claim 15, wherein forming said drain region and said source region comprises forming a spacer element on sidewalls of a gate electrode structure for defining a final offset of said drain region and source region with respect to said gate electrode prior to introducing a dopant species of said first conductivity type.

23. The method of claim 17, further comprising implanting a dopant species of said second conductivity type into said semiconductor region prior to forming said gate electrode structure and laterally asymmetrically increasing a concentration of the species of said second conductivity type during said tilted implantation process to form laterally asymmetrically positioned halo regions.

24. The method of claim 23, wherein forming said drain and source regions comprises positioning a first halo region to form a PN junction with said drain region and positioning a second halo region to be embedded in said source region.