Integrated structure for MEMS device and semiconductor device and method of fabricating the same

• US 20090243004A1
• Filed: 03/27/2008
• Published: 10/01/2009
• Est. Priority Date: 03/27/2008
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Ho, Li-Hsun, Chen, Min, Wu, Wei-Cheng, Wu, Hui-Min, Su, Tzung-I, Lan, Bang-Chiang, Huang, Chien-Hsin
• Granted Patent: US 8,872,287 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00801 Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer B81C1/00595, B81C1/00468 take precedence
• CPC Class Codes: B81C 2201/014 by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout

Abstract

The present invention relates to an integrated structure for a MEMS device and a semiconductor device and a method of fabricating the same, in which an etch stopping device is included on a substrate between the MEMS device and the semiconductor device for protecting the semiconductor device from lateral damage when an oxide releasing process is performed to fabricate the MEMS device. The etch stopping device has various profiles and is selectively formed by an individual fabricating process or is simultaneously formed with the semiconductor device in the same fabricating process. It is a singular structure or a combined stacked multilayered structure, for example, a plurality of rows of pillared etch-resistant material plugs, one or a plurality of wall-shaped etch-resistant material plugs, or a multilayered structure of a stack of which and an etch-resistant material layer.

Claims

1. An integrated structure for a MEMS device and a semiconductor device, comprising:

a substrate;

a dielectric layer formed on the substrate;

a MEMS device formed in the substrate or the dielectric layer;

a semiconductor device formed in the substrate or the dielectric layer; and

an etch stopping device formed on the substrate and in the dielectric layer between the MEMS device and the semiconductor device, thereby to protect the semiconductor device from being etched during a release process for making the MEMS device.

2. The integrated structure for a MEMS device and a semiconductor device of claim 1, wherein the etch stopping device comprises a plurality of pillared etch-resistant material plugs arranged in a plurality of rows.

3. The integrated structure for a MEMS device and a semiconductor device of claim 2, wherein the pillared etch-resistant material plugs comprises an HF-resistant material.

4. The integrated structure for a MEMS device and a semiconductor device of claim 2, wherein the pillared etch-resistant material plugs of the two adjacent rows are arranged in stagger.

5. The integrated structure for a MEMS device and a semiconductor device of claim 2, wherein the etch stopping device further comprises an etch resistant material layer stacked with the pillared etch-resistant material plugs.

6. The integrated structure for a MEMS device and a semiconductor device of claim 5, wherein the etch-resistant material layer stacked with the pillared etch-resistant material plugs together has a dual damascene structure.

7. The integrated structure for a MEMS device and a semiconductor device of claim 1, wherein the etch stopping device comprises at least a wall-shaped etch-resistant material plug.

8. The integrated structure for a MEMS device and a semiconductor device of claim 7, wherein the at least a wall-shaped etch-resistant material plug comprises an HF-resistant material.

9. The integrated structure for a MEMS device and a semiconductor device of claim 7, wherein the etch stopping device further comprises an etch resistant material layer stacked with the at least wall-shaped etch-resistant material plug.

10. The integrated structure for a MEMS device and a semiconductor device of claim 9, wherein the etch-resistant material layer stacked with the at lest a wall-shaped etch-resistant material plug together has a dual damascene structure.

11. The integrated structure for a MEMS device and a semiconductor device of claim 1, wherein the MEMS device is surrounded by the etch stopping device.

12. A method of fabricating an integrated structure for a MEMS device and a semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a MEMS region, an etch stopping device region, and a semiconductor device region, the MEMS region is separated from the semiconductor device region by the etch stopping device region, a transistor is disposed on the substrate in the semiconductor device region, and a first MEMS component is disposed on the substrate in the MEMS region;

performing a interconnect process on the substrate in the semiconductor device region to form a plurality of first dielectric layers, at least a conductive plug and at least a conductive layer in the first dielectric layers;

forming a plurality of second dielectric layers and an etch stopping device in the second dielectric layers on the substrate in the etch stopping device region;

forming a plurality of third dielectric layers and at least a second MEMS component in the third dielectric layers on the substrate in the MEMS region; and

performing an etching process to remove the third dielectric layers in the MEMS region.

13. The method of claim 12, wherein the etch stopping device is formed simultaneously with the at least a conductive plug or the at least a conductive layer when performing the interconnect process.

14. The method of claim 13, wherein the interconnect process comprises a damascene process or a dual damascene process.

15. The method of claim 12, wherein the etch stopping device comprises a plurality of pillared etch-resistant material plugs arranged in a plurality of rows.

16. The method of claim 15, wherein the etch stopping device further comprises an etch resistant material layer stacked with the pillared etch-resistant material plugs.

17. The method of claim 12, wherein the etch stopping device comprises at least a wall-shaped etch-resistant material plug.

18. The method of claim 17, wherein the etch stopping device further comprises an etch resistant material layer stacked with the at least a wall-shaped etch-resistant material plug.

19. The method of claim 12, wherein the at least a second MEMS component and one of the at least a conductive plug and the at least a conductive layer are formed simultaneously when performing the interconnect process.

20. The method of claim 12, wherein the etching process comprises a wet etching or a vapor etching.