SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE MOUNTING STRUCTURE

• US 20090243035A1
• Filed: 03/23/2009
• Published: 10/01/2009
• Est. Priority Date: 03/28/2008
• Status: Abandoned Application

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: MASHINO, Naohiro
• Application Number:
  US12/408,927
• Publication Number:
  US 20090243035A1
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/8121 using a reflow oven
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06531 Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

In a semiconductor device that is formed by joining two semiconductor elements together to oppose device layers to each other, inductor patterns for transmitting and receiving a signal and feeding a power and bumps for connecting electrically the semiconductor elements and for supporting the inductor patterns and the semiconductor elements being arranged opposedly in an electrically isolated state are provided on a surface of the device layer of at least one of semiconductor elements and an electrically insulating material is filled in a space between opposing surfaces of the semiconductor elements.

Claims

1. A semiconductor device comprising:

two semiconductor elements, each having a device layer, the two semiconductor elements being jointed together to oppose the respective device layers to each other, at least one of semiconductor elements having an inductor pattern and a bump on a surface of the device layer, the bump connecting electrically the semiconductor elements and supporting and electrically isolating the inductor pattern and the opposedly arranged semiconductor element; and

an electrically insulating material filled in a space between opposing surfaces of the semiconductor elements.

2. A semiconductor device according to claim 1, wherein the inductor pattern is used for transmitting and receiving a signal or for feeding a power.

3. A semiconductor device according to claim 1, wherein at least one inductor pattern for transmitting and receiving the signal and at least one inductor pattern for feeding the power are provided to the semiconductor elements respectively.

4. A semiconductor device according to claim 1, wherein the semiconductor elements have the inductor patterns on the surfaces of the device layers, respectively, so as to oppose to each other.

5. A semiconductor device according to claim 1, wherein the bump is a solder bump.

6. A semiconductor device according to claim 1, wherein the bump is a gold bump.

7. A semiconductor device according to claim 6, wherein the semiconductor elements have the gold bumps on the surfaces of the device layers, respectively, so as to oppose to each other, and

the electrically insulating material is an anisotropic conductive resin, and the gold bumps provided in opposing positions are connected electrically mutually via the anisotropic conductive resin.

13. A semiconductor device mounting structure, comprising:

a wiring substrate; and

a semiconductor device according to claim 1, mounted on the wiring substrate,

wherein the wiring substrate has another inductor pattern formed in an position opposed in planarly to the inductor pattern provided to the semiconductor device so that an electromagnetic inducing action is produced between the another inductor pattern and the inductor pattern provided to the semiconductor device.

14. A semiconductor device mounting structure, according to claim 13, wherein the another inductor pattern is used for transmitting and receiving a signal or for feeding a power.

15. A semiconductor device mounting structure, according to claim 13, wherein a plurality of the semiconductor device are stacked to form a stacked body, and

the semiconductor devices constituting the stacked body are provided in positions, in which the inductor patterns provided on neighboring semiconductor elements oppose planarly to each other, between the semiconductor devices located in neighboring positions in a stacking direction.

16. A semiconductor device mounting structure, according to claim 15, wherein the inductor patterns provided to the semiconductor devices constituting the stacked body are provided in common positions having same planar positions in all semiconductor devices.

8. A method of manufacturing a semiconductor device, comprising:

a step of forming an inductor pattern on a surface of a device layer formed on a semiconductor wafer;

a step of forming a bump on the surface of the device layer formed on the semiconductor wafer;

a step of arranging two semiconductor wafers, on each of which the inductor pattern and the bump are formed, to oppose respective device layers to each other, and joining the bumps together;

a step of filling an electrically insulating material into a space between opposing surfaces of two semiconductor wafers being joined via the bumps to form a jointed body; and

a step of forming individual semiconductor devices, by dicing the joined body into individual pieces.

9. A method of manufacturing a semiconductor device, according to claim 8, wherein, in the step of forming the bump, a solder bump is formed as the bump, and

in the step of joining the bumps, the bumps are joined by a reflow soldering.

10. A method of manufacturing a semiconductor device, according to claim 8, wherein the inductor pattern is used for transmitting and receiving a signal or for feeding a power.

11. A method of manufacturing a semiconductor device, comprising:

a step of forming an inductor pattern on a surface of a device layer formed on a semiconductor wafer;

a step of forming a gold bump on the surface of the device layer formed on the semiconductor wafer;

a step of interposing an anisotropic conductive resin between opposing surfaces of two semiconductor wafers on each of which the inductor pattern and the gold bump are formed, and connecting electrically the opposing gold bumps and filling the anisotropic conductive resin into a space between the opposing surfaces of the two semiconductor wafers by pressing the two semiconductor wafers from both surface sides to form a jointed body; and

a step of forming individual semiconductor devices, by dicing the joined body into individual pieces.

12. A method of manufacturing a semiconductor device, according to claim 11, wherein the inductor pattern is used for transmitting and receiving a signal or for feeding a power.