REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS

• US 20090243116A1
• Filed: 01/16/2009
• Published: 10/01/2009
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Werner, Thomas, Frohberg, Kai, Feustel, Frank, Grillberger, Michael
• Granted Patent: US 8,357,610 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence.

Claims

1. A method, comprising:

forming a via opening in a low-k dielectric layer formed above a substrate of a semiconductor device;

forming a cap layer on exposed surface portions of said low-k dielectric layer and said via opening;

forming a planarization layer on said cap layer; and

forming a trench in said low-k dielectric layer on the basis of said planarization layer.

2. The method of claim 1, wherein forming said cap layer comprises forming a dielectric material on said exposed surface portions.

3. The method of claim 1, wherein forming said cap layer comprises forming a conductive material on said exposed surface portions and removing a portion of said conductive material outside said via opening after forming said trench.

4. The method of claim 1, further comprising removing said cap layer in said via opening after forming said trench.

5. The method of claim 1, further comprising filling said via opening and said trench with a metal in a common fill process.

6. The method of claim 5, further comprising forming a conductive barrier layer at least in said trench prior to filling said via opening and said trench with a metal.

7. The method of claim 1, further comprising removing said planarization layer after forming said trench and deepening said via opening so as to extend to a metal region.

8. The method of claim 1, wherein said via opening is formed so as to extend to a metal region located below said low-k dielectric layer.

9. The method of claim 8, further comprising forming a conductive barrier layer on a portion of said metal region exposed by said via opening.

10. A method, comprising:

forming a via opening in a first dielectric material of a metallization layer of a semiconductor device;

forming a second dielectric material above said first dielectric material, said second dielectric material filling said via opening;

forming a trench in said second dielectric material so as to connect to said via opening; and

filling said trench and said via opening with a metal in a common fill process.

11. The method of claim 10, wherein forming said trench comprises etching said second dielectric material and using said first dielectric material as an etch stop.

12. The method of claim 11, further comprising forming a conductive barrier layer in said via opening and said trench prior to performing said common fill process.

13. The method of claim 10, wherein forming said second dielectric material comprises applying a low-k dielectric material by performing a spin-on process.

14. The method of claim 10, further comprising forming an etch stop layer on said first dielectric material and within said via opening prior to forming said second dielectric material.

15. The method of claim 14, further comprising removing said etch stop layer from a bottom of said via opening after forming said trench.

16. The method of claim 14, wherein said via opening is formed so as to extend to a surface of a metal region located below said first dielectric material prior to forming said etch stop layer.

17. The method of claim 16, further comprising removing said etch stop layer from said surface prior to performing said common fill process.

18. A semiconductor device, comprising:

a metal region formed in a first dielectric material of a metallization structure; and

a via at least partially formed in a second dielectric material and connected to said metal region, said via comprising, at least on a portion of sidewalls thereof, a dielectric liner comprised of a dielectric material other than said first and second dielectric materials.

19. The semiconductor device of claim 18, wherein said first and second dielectric materials are of the same composition.

20. The semiconductor device of claim 18, wherein said first and second dielectric materials are separated by said dielectric liner.

21. The semiconductor device of claim 20, wherein a bottom of said metal region is formed by said second dielectric material.