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MULTI-POLE DELAY ELEMENT DELAY LOCKED LOOP (DLL)

  • US 20090243672A1
  • Filed: 03/31/2008
  • Published: 10/01/2009
  • Est. Priority Date: 03/31/2008
  • Status: Abandoned Application
First Claim
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1. A delay line comprisinga plurality of cascading delay stages, wherein each delay stage delays the phase of a clock signal a defined amount, wherein each stage includes an active delay device and one or more passive delay devices.

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