MULTI-POLE DELAY ELEMENT DELAY LOCKED LOOP (DLL)
First Claim
1. A delay line comprisinga plurality of cascading delay stages, wherein each delay stage delays the phase of a clock signal a defined amount, wherein each stage includes an active delay device and one or more passive delay devices.
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Abstract
In general, in one aspect, the disclosure describes a delay line including a cascade of delay stages where each stage delays the phase a defined amount. Each delay stage includes an active voltage control delay element and one or more passive delay elements (e.g., resistive-capacitive (RC) networks). The aggregate amplitude gain roll-off of an active/passive multi pole delay stage delaying the phase a defined amount is less than the amplitude gain roll-off of a single pole delay stage delaying the phase the defined amount. Accordingly jitter amplification of the active/passive multi pole delay stage is less than that of a single pole delay stage. The power consumption of an active/passive multi pole delay stage is less than an all active multi pole delay stage.
14 Citations
15 Claims
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1. A delay line comprising
a plurality of cascading delay stages, wherein each delay stage delays the phase of a clock signal a defined amount, wherein each stage includes an active delay device and one or more passive delay devices.
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8. A delay locked loop (DLL) comprising
a phase detector; -
a charge pump; a low pass filter; and a multi-pole delay line having a plurality of cascading delay stages, wherein each delay stage delays the phase of a clock signal a defined amount, wherein each stage includes an active delay device and one or more passive delay devices. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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Specification