BIAS CURRENT GENERATOR

• US 20090243711A1
• Filed: 03/25/2008
• Published: 10/01/2009
• Est. Priority Date: 03/25/2008
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Marinca, Stefan
• Granted Patent: US 7,902,912 B2
• Time in Patent Office: Days
• US Class Current: 327/541
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence

Abstract

A bias current generator for generating bias current is described. The generator comprises an amplifier having an inverting input, a non-inverting input and an output. A first bipolar transistor is associated with one of the inverting and non-inverting inputs of the amplifier. A load MOS device is associated with the other one of the inverting and non-inverting inputs of the amplifier. The load MOS device is driven by the amplifier to operate in the triode region with a corresponding drain-source resistance r_on. The first bipolar transistor and the load MOS device are arranged such that a voltage derived from the first bipolar transistor is developed across the drain-source resistance r_on of the load MOS device thereby generating a bias current.

Claims

1. A bias current generator comprising:

a first amplifier having an inverting input, a non-inverting input and an output,

a first bipolar transistor associated with one of the inverting and non-inverting inputs of the first amplifier,

a load MOS device associated with the other one of the inverting and non-inverting inputs of the first amplifier,

the load MOS device being driven by the first amplifier to operate in the triode region with a corresponding drain-source resistance r_on, the first bipolar transistor and the load MOS device being arranged such that a voltage derived from the first bipolar transistor is developed across the drain-source resistance r_on of the load MOS device thereby generating a bias current.

2. A bias current generator as claimed in claim 1, wherein the voltage developed across the drain-source resistance r_on of the load MOS device corresponds to the base-emitter voltage V_be of the first bipolar transistor thereby generating a CTAT bias current.

3. A bias current generator as claimed in claim 1, wherein the generator further comprises a second bipolar transistor operating at a lower collector current density than that of the first bipolar transistor, the first and second bipolar transistors being arranged relative to the load MOS device such that the voltage developed across the drain-source resistance r_on of the load MOS device corresponds to the base-emitter voltage difference Δ

V_be between the first bipolar transistor and the second bipolar transistor thereby generating a PTAT bias current.

4. A bias current generator as claimed in claim 1, wherein the generator further comprises a biasing MOS device operably coupled to the load MOS device for facilitating biasing the load MOS to operate in the triode region.

5. A bias current generator as claimed in claim 4, wherein the biasing MOS device operates in the saturation region.

6. A bias current generator as claimed in claim 5, wherein the biasing MOS device is in a diode configuration.

7. A bias current generator as claimed in claim 6, wherein the diode configured MOS device is arranged in a cascoded arrangement relative to the load MOS device.

8. A bias current generator as claimed in claim 6, wherein the gate of the load MOS device is coupled to the gate of the diode configured MOS device.

9. A bias current generator as claimed in claim 6, wherein at least one trimming MOS device is coupled in parallel with the diode configured MOS device.

10. A bias current generator as claimed in claim 9, wherein the bias current generator further comprises a switch for selectively coupling the gate of the trimming device to one of the drain and source of the diode configured MOS device.

11. A bias current generator as claimed in claim 10, wherein the switch comprises a CMOS inverter operably coupled between the drain and source of the diode configured MOS device.

12. A bias current generator as claimed in claim 1, wherein the bias current generator further comprises a current mirror arrangement driven by the first amplifier for mirroring the generated bias current.

13. A bias current generator as claimed in claim 12, wherein the current mirror arrangement comprises a plurality of PMOS devices.

14. A bias current generator as claimed in claim 13, wherein the current mirror arrangement comprises at least two NMOS transistors one of which is associated with the load MOS device for receiving the generated bias current.

15. A bias current generator as claimed in claim 14, wherein the generator further comprises a second amplifier including an inverting input, non-inverting input and an output, the two NMOS transistors of the current mirror arrangement are coupled to the corresponding inputs of the second amplifier such that their drain source voltages are substantially similar.

16. A bias current generator as claimed in claim 14, wherein the output of the first amplifier drives the gates of the two NMOS transistors of the current mirror arrangement.

17. A bias current generator as claimed in claim 15, wherein the output of the second amplifier drives the gates of the PMOS transistors of the current mirror arrangement.

18. A bias current generator as claimed in claim 4, wherein the load and biasing MOS devices have different aspect ratios.

19. A bias current generator as claimed in claim 18, wherein the aspect ratio of the load MOS device is greater than the aspect ratio of the biasing MOS device.

20. A bias current generator as claimed in claim 4, wherein the first amplifier further comprises inverting and non-inverting outputs each driving a corresponding one of the load and biasing MOS devices.

21. A bias current generator as claimed in claim 20, wherein the inverting output drives the gate of load MOS device, and the non-inverting output drives the gate of the biasing MOS transistor.

22. A bias current generator comprising:

an amplifier having an inverting input, a non-inverting input and an output,

a bipolar transistor associated with one of the inverting and non-inverting inputs of the amplifier,

a load MOS device associated with the other one of the inverting and non-inverting inputs of the amplifier,

the load MOS device being driven by the amplifier to operate in the triode region with a corresponding drain-source resistance r_on, the bipolar transistor and the load MOS device being arranged such that the voltage developed across the drain-source resistance r_on of the load MOS device corresponds to the base-emitter voltage V_be of the bipolar transistor thereby generating a CTAT bias current.

23. A bias current generator comprising:

an amplifier having an inverting input, a non-inverting input and an output,

a first bipolar transistor associated with one of the inverting and non-inverting inputs of the amplifier,

a load MOS device associated with the other one of the inverting and non-inverting inputs of the amplifier, and

a second bipolar transistor operating at a lower collector current density than that of the first bipolar transistor and being associated with the load MOS device such that a base-emitter voltage difference Δ

V_be between the first bipolar transistor and the second bipolar transistor is developed across the drain-source resistance r_on of the load MOS thereby generating a PTAT bias current.