Device for reducing power consumption inside integrated circuit

• US 20090243712A1
• Filed: 02/11/2009
• Published: 10/01/2009
• Est. Priority Date: 04/01/2008
• Status: Abandoned Application

• Current Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Original Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Inventors: Chiang, Yun-Chi
• Application Number:
  US12/378,113
• Publication Number:
  US 20090243712A1
• Time in Patent Office: Days
• US Class Current: 327/541
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

The present invention discloses a device for reducing power consumption inside an integrated circuit (IC), comprising: an IC including an up-gate transistor and a low-gate transistor electrically connected with each other, and a control circuit controlling the up-gate transistor and the low-gate transistor; and a resistor located outside the IC, the resistor having one end electrically connected with a node between the up-gate transistor and the low-gate transistor, or electrically connected with an upper end of the up-gate transistor.

Claims

1. A device for reducing power consumption inside an integrated circuit (IC), comprising:

an IC including an up-gate transistor and a low-gate transistor electrically connected with each other, and a control circuit controlling the up-gate transistor and the low-gate transistor; and

a first resistor located outside the IC, the first resistor having one end electrically connected with a node between the up-gate transistor and the low-gate transistor.

2. The device of claim 1, wherein the other end of the first resistor is electrically connected with a voltage output node.

4. The device of claim 1, further comprising a second resistor located outside the IC, the second resistor being electrically connected with an upper end of the up-gate transistor.

5. The device of claim 2, wherein the low-gate transistor is turned OFF according to a voltage at the voltage output node.

3. The device of claim L, wherein the IC is a liquid crystal display power management circuit or a switching regulator.

6. A device for reducing power consumption inside an integrated circuit (IC), comprising:

an IC including an up-gate transistor and a low-gate transistor electrically connected with each other, and a control circuit controlling the up-gate transistor and the low-gate transistor; and

a first resistor located outside the IC, the first resistor having one end electrically connected with an upper end of the up-gate transistor.

7. The device of claim 6, wherein the other end of the first resistor is electrically connected with a voltage supply.

8. The device of claim 6, wherein the IC is a liquid crystal display power management circuit or a switching regulator.

9. The device of claim 6, further comprising a second resistor located outside the IC, the second resistor having one end electrically connected with a node between the up-gate transistor and the low-gate transistor.

10. The device of claim 9, wherein the other end of the second resistor is electrically connected with a voltage output node, and wherein the low-gate transistor is turned OFF according to a voltage at the voltage output node.