DEMODULATION CIRCUIT

• US 20090243716A1
• Filed: 06/10/2009
• Published: 10/01/2009
• Est. Priority Date: 03/14/2007
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: YAMAZAKI, Daisuke, Radecki, Andrzej
• Granted Patent: US 8,022,754 B2
• Time in Patent Office: Days
• US Class Current: 329/369
• CPC Class Codes: H03D 1/10 of diodes
• CPC Class Codes: H03D 1/18 of semiconductor devices
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits

Abstract

A demodulation circuit, including: an input terminal (IN) inputting a current amplitude modulated signal; a first transistor (101) connected to the input terminal; a capacitance (105) connected to a control terminal of the first transistor; a diode (102) connected between the input terminal and the control terminal of the first transistor; and a first current source (104) applying a current of the input terminal, is provided.

Claims

1. A demodulation circuit, comprising:

an input terminal inputting a current amplitude modulated signal;

a first transistor connected to said input terminal;

a capacitance connected to a control terminal of said first transistor;

a diode connected between said input terminal and the control terminal of said first transistor; and

a first current source applying a current of said input terminal.

2. The demodulation circuit according to claim 1, further comprising:

a first comparator comparing a voltage of said input terminal and a voltage of the control terminal of said first transistor.

3. The demodulation circuit according to claim 1, wherein

said diode is constituted by a field-effect transistor of which gate and drain are mutually connected.

4. The demodulation circuit according to claim 1, wherein

said first current source is connected to the control terminal of said first transistor.

5. The demodulation circuit according to claim 4, wherein

said first current source is constituted by a field-effect transistor of which gate and drain are connected to the control terminal of said first transistor.

6. The demodulation circuit according to claim 2, further comprising:

a switch interrupting the current flowing in said first current source in accordance with a comparison result of said first comparator.

7. The demodulation circuit according to claim 2, further comprising:

an abnormality detector lowering the voltage of the control terminal of said first transistor when a time when the voltage of said input terminal is lower than the voltage of the control terminal of said first transistor is longer than a threshold value.

8. The demodulation circuit according to claim 7, wherein

said abnormality detector includes:

a timer outputting a voltage in accordance with the time when the voltage of said input terminal is lower than the voltage of the control terminal of said first transistor;

a second comparator comparing the voltage outputted from the timer and a threshold value; and

a switch connecting the control terminal of said first transistor to a reference potential in accordance with a comparison result of the second comparator.

9. The demodulation circuit according to claim 1, further comprising:

a second current source connected to the control terminal of said first transistor, wherein

said first current source is connected to said input terminal.

10. The demodulation circuit according to claim 9, wherein

a size of the current in said first current source is controlled in accordance with the voltage of the control terminal of said first transistor.

11. The demodulation circuit according to claim 9, wherein

said first current source is constituted by a field-effect transistor of which gate is connected to the control terminal of said first transistor and drain is connected to said input terminal.

12. The demodulation circuit according to claim 11, wherein

a drain of the field-effect transistor is connected to said input terminal via a load.

13. The demodulation circuit according to claim 2, wherein

said diode is constituted by a field-effect transistor of which gate and drain are mutually connected.

14. The demodulation circuit according to claim 13, wherein

said first current source is constituted by a field-effect transistor of which gate and drain are connected to the control terminal of said first transistor.

15. The demodulation circuit according to claim 14, further comprising:

a first switch interrupting the current flowing in said first current source in accordance with a comparison result of said first comparator.

16. The demodulation circuit according to claim 15, further comprising:

an abnormality detector lowering the voltage of the control terminal of said first transistor when a time when the voltage of said input terminal is lower than the voltage of the control terminal of said first transistor is longer than a threshold value.

17. The demodulation circuit according to claim 16, wherein

said abnormality detector includes:

a timer outputting a voltage in accordance with the time when the voltage of said input terminal is lower than the voltage of the control terminal of said first transistor;

a second comparator comparing the voltage outputted from the timer and a threshold value; and

a second switch connecting the control terminal of said first transistor to a reference potential in accordance with a comparison result of the second comparator.

18. The demodulation circuit according to claim 2, further comprising:

a second current source connected to the control terminal of said first transistor, wherein

said first current source is connected to said input terminal.

19. The demodulation circuit according to claim 18, wherein

said first current source is constituted by a field-effect transistor of which gate is connected to the control terminal of said first transistor, and drain is connected to said input terminal.

20. The demodulation circuit according to claim 19, wherein

a drain of the field-effect transistor is connected to said input terminal via a load.