VARIABLE RESISTOR ARRAY AND AMPLIFIER CIRCUIT

• US 20090243726A1
• Filed: 03/16/2009
• Published: 10/01/2009
• Est. Priority Date: 04/01/2008
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: KOJIMA, Takashi
• Granted Patent: US 7,868,694 B2
• Time in Patent Office: Days
• US Class Current: 330/282
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03G 3/001 Digital control of analog signals

Abstract

A variable resistor array adapted to make a resistance value between a first terminal and a second terminal variable, includes a plurality of resistors connected in series, first through nth MOS transistors selectively connected to the resistors, and first through nth switches having one input terminal connected to the source of the ith MOS transistor, another input terminal connected to a predetermined voltage, and an output terminal connected to a back gate of the ith MOS transistor, and connecting either one of the one input terminal and the other input terminal to the output terminal under control of the ith control signal. The ith switch connects the other input terminal to the output terminal, and the ith switch also connects the one input terminal to the output terminal.

Claims

1. A variable resistor array

(1) adapted to make a resistance value between a first terminal and a second terminal variable, comprising:

(2) first through nth resistors (n is an integer equal to or greater than 2, the same applies hereinafter) connected in series, one end of the first resistor being connected to the second terminal, another end of ith one (i is an integer equal to or greater than 1 and equal to or smaller than (n−

1), the same applies hereinafter) of the resistors and the one end of (i+1)th one of the resistors being connected to each other;

(3) first through nth MOS transistors, ith one of the MOS transistors having a drain connected to a connection point between the ith resistor and the (i+1)th resistor, a source connected to the first terminal, and a gate receiving an input of ith one of first through nth control signals, and nth one of the MOS transistors having a drain connected to the other end of the nth resistor; and

(4) first through nth switches, ith one of the switches having one input terminal connected to the source of the ith MOS transistor, another input terminal connected to a predetermined voltage, and an output terminal connected to a back gate of the ith MOS transistor, and connecting either one of the one input terminal and the other input terminal to the output terminal under control of the ith control signal,

(5) wherein (5a) in accordance with the ith control signal being at an ON voltage for making the ith MOS transistor conductive, the ith switch connects the other input terminal to the output terminal, thereby applying a voltage of the source to the back gate of the ith MOS transistor, and the ith MOS transistor becomes conductive in response to the ON voltage applied to the gate, and

(5b) in accordance with the ith control signal being at an OFF voltage for making the ith MOS transistor cut-off, the ith switch connects the one input terminal to the output terminal, thereby applying a predetermined voltage to the back gate of the ith MOS transistor, and the ith MOS transistor becomes cut-off in response to the OFF voltage applied to the gate.

3. An amplifier circuit comprising:

the variable resistor array according to claim 1; and

an amplifier having one of an input terminal and an output terminal connected to the first terminal of the variable resistor array, and the other of the input terminal and the output terminal connected to the second terminal of the variable resistor array.

2. A variable resistor array

(1) adapted to make a resistance value between a first terminal and a second terminal variable, comprising:

(2) first through nth resistors (n is an integer equal to or greater than 2, the same applies hereinafter) connected in parallel to each other, one ends of the first through nth resistors being connected to the second terminal;

(3) first through nth MOS transistors, ith one (i is an integer equal to or greater than 1 and equal to or smaller than (n−

1), the same applies hereinafter) of the MOS transistors having a drain connected to another end of ith one of the resistors, a source connected to the first terminal, and a gate receiving an input of ith one of first through nth control signals; and

(4) first through nth switches, ith one of the switches having one input terminal connected to the source of the ith MOS transistor, another input terminal connected to a predetermined voltage, and an output terminal connected to a back gate of the ith MOS transistor, and connecting either one of the one input terminal and the other input terminal to the output terminal under control of the ith control signal,

(5) wherein (5a) in accordance with the ith control signal being at an ON voltage for making the ith MOS transistor conductive, the ith switch connects the one input terminal to the output terminal, thereby applying a voltage of the source to the back gate of the ith MOS transistor, and the ith MOS transistor becomes conductive in response to the ON voltage applied to the gate, and

(5b) in accordance with the ith control signal being at an OFF voltage for making the ith MOS transistor cut-off, the ith switch connects the other input terminal to the output terminal, thereby applying a predetermined voltage to the back gate of the ith MOS transistor, and the ith MOS transistor becomes cut-off in response to the OFF voltage applied to the gate.