SDOC with FPHA & FPXC: System Design On Chip with Field Programmable Hybrid Array of FPAA, FPGA, FPLA, FPMA, FPRA, FPTA and Frequency Programmable Xtaless ClockChip with Trimless/Trimfree Self-Adaptive Bandgap Reference Xtaless ClockChip

• US 20090243732A1
• Filed: 04/13/2009
• Published: 10/01/2009
• Est. Priority Date: 08/05/2006
• Status: Active Grant

• Current Assignee: Alfred Yu-Chi Tarng, Angela Yu-Shiu Tarng, Eric Yu-Shiao Tarng, Huang Chang Tarng, Jwu-Ing Tarng, Mei Jech Lin, Min Ming Tarng, Shun Y.U. Nieh
• Original Assignee: Alfred Yu-Chi Tarng, Angela Yu-Shiu Tarng, Eric Yu-Shiao Tarng, Huang Chang Tarng, Jwu-Ing Tarng, Mei Jech Lin, Min Ming Tarng, Shun Y.U. Nieh
• Inventors: Tarng, Huang Chang, Nieh, Shun Yu, Tarng, Min Ming, Lin, Mei Jech, Tarng, Angela Yu-Shiu, Tarng, Alfred Yu-Chi, Tarng, Eric Yu-Shiao, Tarng, Jwu-Ing
• Granted Patent: US 8,487,653 B2
• Time in Patent Office: Days
• US Class Current: 331/18
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/1215 the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/124 the means comprising a voltage dependent capacitance
• CPC Class Codes: H03B 5/1253 the transistors being field-effect transistors
• CPC Class Codes: H03B 5/1278 the parameter being an amplitude of a signal, e.g. maintaining a constant output amplitude over the frequency range
• CPC Class Codes: H03B 5/366 and comprising means for varying the frequency by a variable voltage or current
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply
• CPC Class Codes: H03L 1/022 by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature H03L1/021 takes precedence
• CPC Class Codes: H03L 1/026 by using a memory for digitally storing correction values H03L1/025 takes precedence
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop

Abstract

The Field Programmable Hybrid Array (FPHA) and Frequency Programmable Xtaless Clock (FPXC) are for high-speed and high frequency System-Design-On-Chip(SDOC). The FPXC adopts the Self-Adaptive Process & Temperature Compensation Bandgap Reference Generator, the Gain-Boost Amplitude Control LC VCO and inverter type flash memory. The FPHA adopts the two-way flash switch and inverter type flash memory Look-Up-Table(LUT). The FPXC adopts the inverter type flash memory as the Non-Volatile Memory(NVM) to keep the setup data in the field frequency programming. The flash technology of FPHA and FPXC are compatible that the FPHA has the FPXC capability. The PLLess CDR(PLL free Clock Data Recovery) is based on the FPXC capability for the SerDes high frequency application. The PLLess CDR and pipeline ADC are for the analog front high frequency application. With the SDOC on FPHA, the Automobile Infotainment Center(MIC) is reduced to be Mobile Infotainment Center(MIC). The (1) Capacitorless Low Drop Voltage (Capless LDVR) (2) Inductor less Switch Mode Power Supply (Indless SMPS) (3) Resistorless Current Sensor (Resless CS), (4) Saw Filter Less Low Noise Amplifier(Sawless LNA), (5) Diode Less True Random Number Generator (Dioless TRNG), (6) Crystal Less Clock (Xtaless Clock), (7) PLL Less Clock and Data Recovery (PLLess CDR) and (8) Filmless Touching Screen (FLTS) constitutes the most advanced System Design On Chip (SDOC) on Field Programmable Hybrid Array (FPHA) for Mobile Infotainment Center (MIC).

Claims

1. A system design on chip means comprising frequency programmable means,

sending a reference clock signal means into said frequency programmable means,

said frequency programmable means further comprising programmable frequency controlling means,

said programmable frequency controlling means adjusting a self-adaptive resonator means to have oscillator frequency being locked with said reference clock signal means.

4. A system design on chip means according to claim 1 further comprising a self-adaptive process and temperature compensation bandgap reference circuit means,

said self-adaptive process and temperature compensation bandgap reference circuit means generating process-independent and temperature-independent voltage means and current means from bandgap reference circuit means with process compensation and temperature compensation.

5. A system design on chip means according to claim 4, said self-adaptive process and temperature compensation bandgap reference circuit means further comprising variable resistance means, said variable resistance means being parallel connection of switching means and resistance means;

said variable resistance means being reverse proportional to variation of said reference voltage means and reference current means;

said variable resistors being switching means parallel with resistors means, as said reference voltage means and current means increasing, said switching means being reverse proportional tuned off to increase resistance of said variable resistors.

said self-adaptive process and temperature compensation bandgap reference circuit means further comprising a first diode means, a second diode means in series with a first variable resistor means,

a second variable resistor means being in parallel with said first diode means;

a third variable resistor means being in parallel with said first diode means and said third variable resistor means being equal to said second variable resistor;

said first variable resistor being for adjustment of proportional to absolute temperature PTAT variation;

said second and third variable resistors being for complimentary to absolute temperature CTAT variation;

resistances of said first variable resistor, said second and third variable resistors being proportional to said reference current means and voltage means.

13. A system design on chip means according to claim 1 further comprising a PLLess CDR means,

said PLLess CDR means further comprising a sampler;

said sampler sampling data and getting early and late information;

said early and late feedback to said self-adaptive resonator means to adjust phase and frequency of said self-adaptive resonator means.

said self-adaptive resonator being able to adjust phase and frequency separately.

2. A system design on chip means comprising flash switch means,

said flash switch means having a first isolated gate means to store charges;

said flash switch means further comprising a charging and discharging plate means,

electron charges means being able to transfer from or transfer to said charging and discharging plate means to said isolated gate means.

6. A system design on chip means according to claim 2 further comprising an inverter means, a lock device means and initial means to be a flash memory means,

said inverter means reading output of said flash switch means and controlling said lock device means to cooperate with said flash switch means to lock a state of said flash memory means;

said initial means initializing said state of said flash memory means.

7. A system design on chip means according to claim 2 of which said charging plate means comprising a first peak means;

isolated gate means comprising a second peak means;

said first peak means transferring charging means from said charging plate means to said isolated gate means;

said second peak means transferring charging means from said isolated gate means to said charging plate means;

said first peak means and said second peak means also being able to be edge means of said charging plate means and isolated gate means.

9. A system design on chip means according to claim 2 of which said flash switch means further comprising a sensing means,

said sensing means having a second isolated gate means which being in common with said first isolated gate means;

said sensing means sensing state of said flash switch means.

11. A system design on chip means according to claim 2 of which said flash switch means further comprising a bias plate means,

said first isolated gate means being between said bias plate and charging plate means;

said bias plate means helping two-way charge transferring between said first isolated gate and charging plate means.

14. A system design on chip means according to claim 2 further comprising filmless touching screen means, said filmless touching screen means having conductive layer being deposed in touching screen.

15. A system design on chip means according to claim 17 of which said conductive layer being in one dimensional.

16. A system design on chip means according to claim 18 further comprises a capacitance detector means,

said capacitance detector means comprising a charging switch and discharging switch at the two ends of the conductive layer, said charging switch charging said conductive layer;

said discharging switch discharging said conductive layer to detect voltage variance over time to detect coordinate of touching position.

17. A system design on chip means according to claim 2 further comprising field programmable hybrid array having pipeline architecture.

18. A system design on chip means according to claim 19 further comprising analog buffer means and digital buffer means.

19. A system design on chip means according to claim 2 further comprising field programmable hybrid switch made of analog buffer means and digital buffer means.

20. A system design on chip means according to claim 2 further comprising a system design on chip methodology being compatible with a system design on board methodology.

3. A system design on chip means comprising flash memory means,

said flash memory means comprising PMOS means and NMOS means in inverter type connection,

said flash memory means having a first isolated gate means to store charges;

said flash memory means further comprising a charging and discharging plate means,

electron charges means being able to transfer from or transfer to said charging and discharging plate means to said first isolated gate means.

8. A system design on chip means according to claim 3 of which said charging plate means comprising a first peak means;

isolated gate means comprising a second peak means;

said first peak means transferring charging means from said charging plate means to said isolated gate means;

said second peak means transferring charging means from said isolated gate means to said charging plate means;

said first peak means and said second peak means also being able to be edge means of said charging plate means and isolated gate means.

10. A system design on chip means according to claim 3 of which said flash memory means further comprising a sensing means,

said sensing means having a second isolated gate means which being in common with said first isolated gate means;

said sensor means sensing state of said flash memory means.

12. A system design on chip means according to claim 3 of which said flash memory means further comprising a bias plate means,

said first isolated gate means being between said bias plate and charging plate means;

said bias plate means helping two-way charge transferring between said first isolated gate and charging plate means.