PROCESS VARIATION BASED MICROCHIP IDENTIFICATION
First Claim
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1. An apparatus comprising:
- a multiplexer circuit configured to generate an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal;
a plurality of bit generation circuits each configured to generate one of said plurality of input bits; and
a control circuit configured to generate said control signal.
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Abstract
An apparatus comprising a multiplexer circuit, a plurality of bit generation circuits, and a control circuit. The multiplexer circuit may be configured to generate an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal. The plurality of bit generation circuits may each be configured to generate one of the plurality of input bits. The control circuit may be configured to generate the control signal.
14 Citations
18 Claims
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1. An apparatus comprising:
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a multiplexer circuit configured to generate an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal; a plurality of bit generation circuits each configured to generate one of said plurality of input bits; and a control circuit configured to generate said control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for generating a chip identification, comprising the steps of:
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(A) generating an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal; (B) generating a plurality of input bits in response to a plurality of bit generation circuits; and (C) generating said control signal. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method for generating a bit pattern, comprising the steps of:
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(A) generating a plurality of bits; (B) generating a first count value indicating a number of times a first digital value is generated within said plurality of bits; (C) generating a second count value indicating a number of times a second digital value is generated within said plurality of bits; (D) if said first count value and said second count value are within a predetermined tolerance, storing said bit pattern; and (E) repeating steps (A) through (D) if said first count value and said second count value are not within a predetermined tolerance. - View Dependent Claims (18)
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Specification