Analog-to-digital converter

• US 20090243907A1
• Filed: 09/15/2008
• Published: 10/01/2009
• Est. Priority Date: 02/02/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: ClariPhy Communications Incorporated (Inphi Corporation)
• Inventors: Asmanis, Georgios, Luna, German, Kargar, Mahyar, Ramprasad, Sumant, Grace, Carl, Nazemi, Ali
• Granted Patent: US 8,094,056 B2
• Time in Patent Office: Days
• US Class Current: 341/161
• CPC Class Codes: H03M 1/1042 the look-up table containing corrected values for replacing the original digital values H03M1/1052 takes precedence
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.

Claims

1. An ADC pipeline unit for converting input analog values to N-bit digital representations, the ADC pipeline unit implemented as a single integrated circuit and comprising:

M lookahead pipeline stages, each lookahead pipeline stage generating 1 raw bit for a total of M raw bits, with M>

N, the stages including open-loop residue amplifiers; and

a calibration unit coupled to the lookahead pipeline stages to compensate for non-linearity in the open-loop residue amplifiers.

2. The ADC pipeline unit of claim 1 wherein the lookahead pipeline stages include comparators that generate the 1 raw bit for the stages, the comparators including offset trimming circuits that trim an input of the comparator to compensate for a nominal offset of the comparator.

3. The ADC pipeline unit of claim 2 wherein the offset trimming circuit comprises:

a digitally programmable current source that provides an offset current to the input of the comparator, the offset current programmable by a digital code input to the current source; and

a state machine that determines and provides the digital code input to the current source.

4. The ADC pipeline unit of claim 3 wherein the state machine shorts the input of the comparator and cycles through the possible digital codes to determine the digital code input to the current source.

5. The ADC pipeline unit of claim 1 further comprising:

a resistor trimming circuit having electrical ports for connection to an off-chip resistor R4 used for calibration, wherein the lookahead pipeline stages include digitally programmable resistors that are trimmed by the resistor trimming circuit.

6. The ADC pipeline unit of claim 5 wherein the resistor trimming circuit comprises:

a digitally programmable resistor R3 coupled to one of the electrical ports, resistors R3 and R4 forming a voltage divider;

resistors R1 and R2 that form a second voltage divider; and

a state machine that sends a digital code to adjust the programmable resistor R3 based on the outputs of the two voltage dividers and trims the digitally programmable resistors in the lookahead pipeline stages based on adjustment of the programmable resistor R3.

7. The ADC pipeline unit of claim 6 wherein the resistor trimming circuit further comprises:

a comparator coupled to compare the outputs of the two voltage dividers, the state machine adjusting the programmable resistor R3 based on an output of the comparator.

8. The ADC pipeline unit of claim 7 wherein the state machine determines the digital code that matches the outputs of the two voltage dividers based on the output of the comparator and sends that digital code to trim the digitally programmable resistors in the lookahead pipeline stages.

9. The ADC pipeline unit of claim 1 wherein the open-loop residue amplifiers comprise:

source followers.

10. The ADC pipeline unit of claim 9 wherein the open-loop residue amplifiers further comprise:

a resistively loaded amplifier that drives the source followers; and

NFET switches in a deep N well driven by the source followers.

11. The ADC pipeline unit of claim 1 wherein the M lookahead pipeline stages comprise:

an input sample-and-hold stage for receiving the input analog value;

a first lookahead pipeline half-stage coupled to the input sample-and-hold, for producing a first raw bit; and

M−

1 lookahead pipeline stages coupled in series to the first lookahead pipeline half-stage, each lookahead pipeline stage producing an additional raw bit;

wherein each of the half-stage and the first M−

2 stages includes an open-loop residue amplifier.

12. The ADC pipeline unit of claim 11 wherein:

the first lookahead pipeline half-stage includes a single comparator for determining the first raw bit; and

each of the M−

1 lookahead pipeline stages includes two comparators, one comparator for determining the raw bit for the stage assuming that the raw bit from a previous stage was 0 and another comparator for determining the raw bit for the stage assuming that the raw bit from the previous stage was 1.

13. The ADC pipeline unit of claim 1 wherein the lookahead pipeline stages can operate at a conversion rate of 1.25 GS/s or higher at an effective resolution of at least 5 bits per sample.

14. The ADC pipeline unit of claim 1 wherein the lookahead pipeline stages can operate at a quantization energy of 0.3 pJ/conv-step or less.

15. The ADC pipeline unit of claim 1 wherein N≧

8.

16. The ADC pipeline unit of claim 1 wherein N≧

5.