FLASH MEMORY DEVICE HAVING DUMMY CELLS AND METHOD OF OPERATING THE SAME

• US 20090244967A1
• Filed: 03/19/2009
• Published: 10/01/2009
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Moo-Sung, LIM, Young-Ho
• Granted Patent: US 8,218,365 B2
• Time in Patent Office: Days
• US Class Current: 365/185.200
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 Reference cells

Abstract

Disclosed is a flash memory device having multiple strings, where each string includes first memory cells and second memory cells. One second memory cell of the second memory cells in each string is set to a programmed state, and remaining second memory cells are set to an erased state.

Claims

1. A flash memory device comprising:

a plurality of strings, each string comprising first memory cells and second memory cells,

wherein one second memory cell of the second memory cells in each string is set to a programmed state, and remaining second memory cells are set to an erased state.

2. The flash memory device of claim 1, wherein the second memory cells are dummy cells.

3. The flash memory device of claim 1, wherein one of the second memory cells is set to a programmed state and second memory cells of other strings, in a same row as the one of the second memory cells, are set to an erased state.

4. The flash memory device of claim 1, wherein during a read/verify operation, a read voltage is applied to the second memory cells set to the programmed state.

5. The flash memory device of claim 4, wherein during the read/verity operation, the plurality of strings are pre-charged simultaneously.

6. The flash memory device of claim 5, wherein the plurality of strings are read N times, wherein N is equal to a number of second memory cells in each string.

7. The flash memory device of claim 1, wherein the second memory cells in each of the plurality of strings are selectively programmed after an erase/verify operation.

8. The flash memory device of claim 1, wherein the number of the second memory cells is determined according to a read frequency.

9. A method of operating a flash memory device, comprising a plurality of strings, the method comprising:

pre-charging the plurality of strings at the same time, each string having first memory cells and second memory cells;

sensing first strings of the plurality of strings; and

sensing second strings of the plurality of strings,

wherein one of the second memory cells in each of the strings is set to a programmed state and each of remaining second memory cells is set to an erased state.

10. The method of claim 9, wherein the second memory cells comprise dummy cells.

11. The method of claim 9, wherein one of the second memory cells is set to a programmed state and each of remaining second memory cells in a same row as the one of the second memory cells is set to an erased state.

12. The method of claim 9, further comprising:

applying a read voltage to the second memory cells set to the programmed state during a read/verify operation.

13. The method of claim 9, wherein the number of the second memory cells is determined according to a read frequency.

14. The method of claim 9, further comprising:

a read operation and a verify operation.