Method for Training Dynamic Random Access Memory (DRAM) Controller Timing Delays

• US 20090244997A1
• Filed: 03/31/2008
• Published: 10/01/2009
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Searles, Shawn, Housty, Oswin, Hamilton, Thomas H., Askar, Tahsin
• Granted Patent: US 7,924,637 B2
• Time in Patent Office: Days
• US Class Current: 365/194
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value are trained (540). A right edge of passing receive enable delay values is determined using a working value of the receive data strobe delay (550); and a final receive enable delay value intermediate between the left edge of passing receive enable delay values and the right edge of passing receive enable delay values is set (560).

Claims

1. A method of training a receive enable delay in a double data rate (DDR) dynamic random access memory (DRAM) controller, comprising:

writing a plurality of data elements in a burst cycle to a burst address over a memory interface for storage in a DRAM;

performing a read burst cycle from said burst address over said memory interface using a receive enable delay value to retrieve a plurality of measured data values;

comparing one of said plurality of measured data values that is not a first one of said plurality of measured data values to a corresponding one of said plurality of data elements; and

determining whether said receive enable delay value is a pass receive enable delay value based on said comparing.

2. The method of claim 1, wherein said burst data cycle comprises four beats, and said comparing comprises:

comparing a third one of said plurality of measured data values to a corresponding third one of said plurality of data elements.

3. The method of claim 1, wherein said burst data cycle comprises four beats, and said comparing comprises:

comparing a second one of said plurality of measured data values to a corresponding second one of said plurality of data elements.

4. The method of claim 1, further comprising:

repeating said performing said read burst cycle, said comparing, and said determining for a plurality of receive enable delay values; and

determining a left edge of passing receive enable delay values in response to said repeating.

5. The method of claim 4, further comprising training a receive data strobe delay value and a transmit data delay value after said determining said left edge of passing receive enable delay values in response to said repeating.

6. The method of claim 5, wherein said training said receive data strobe delay comprises:

writing a plurality of data elements in a burst cycle starting at an initial burst address over a memory interface for storage in a DRAM, wherein alternating ones of said plurality of data elements have different values;

for each of a plurality of values of the receive data strobe delay;

performing a read burst cycle starting at said initial burst address over said memory interface using a selected receive enable delay value to retrieve a measured data value;

comparing said measured data value to an expected value of a corresponding one of said plurality of data elements to provide a first comparison result; and

comparing said measured data value to an expected value of a corresponding next one of said plurality of data elements to provide a second comparison result, and

determining a final receive data strobe delay value using said first and second comparison results.

7. The method of claim 6, further comprising:

for each of a plurality of transmit data delay values;

writing a second plurality of data elements in a burst cycle starting at said initial burst address over said memory interface for storage in said DRAM using a corresponding one of said plurality of transmit data delay values;

performing a second read burst cycle starting at said initial burst address over said memory interface using said final receive data strobe delay value to retrieve a second measured data value; and

comparing said second measured data value to an expected value of a corresponding one of said second plurality of data elements to provide a third comparison result, and

determining a final transmit data delay value using said third comparison result for each of said plurality of transmit data delay values to determine a final transmit data delay value.

8. The method of claim 5, further comprising:

determining a right edge of passing receive enable delay values.

9. The method of claim 8, wherein said determining said right edge of passing receive enable delay values comprises:

adding a half of a unit interval to said left edge of passing receive enable delay values to obtain a working value of said receive enable delay; and

determining said right edge of passing receive enable delay values by starting with said working value.

10. The method of claim 4, further comprising:

determining a right edge of passing receive enable delay values; and

setting a final receive enable delay value in response to said determining said left edge of passing receive enable delay values and said determining said right edge of passing receive enable delay values.

11. The method of claim 10, wherein said setting comprises:

setting said final receive enable delay value substantially halfway between said left edge of passing receive enable delay values and said right edge of passing receive enable delay values.

12. The method of claim 1, further comprising storing a plurality of instructions for said writing, said performing said read burst cycle, said comparing, and said determining in a basic input-output system (BIOS) memory.

13. A method of training a receive data strobe delay in a double data rate (DDR) dynamic random access memory (DRAM) controller, comprising:

writing a plurality of data elements in a burst cycle starting at an initial burst address over a memory interface for storage in a DRAM, wherein alternating ones of said plurality of data elements have different values;

for each of a plurality of values of the receive data strobe delay;

performing a read burst cycle starting at said initial burst address over said memory interface using a selected receive enable delay value to retrieve a measured data value;

comparing said measured data value to an expected value of a corresponding one of said plurality of data elements to provide a first comparison result; and

comparing said measured data value to an expected value of a corresponding next one of said plurality of data elements to provide a second comparison result, and

determining a final receive data strobe delay value using said first and second comparison results.

14. The method of claim 13, wherein said determining comprises:

forming a first mapping of said first comparison result of each of said plurality of values of the receive data strobe delay;

forming a second mapping of said second comparison result of each of said plurality of values of the receive data strobe delay;

concatenating said first mapping after an end of said second mapping to provide a final mapping; and

determining said final receive data strobe delay value using said final mapping.

15. The method of claim 14, wherein said determining said final receive data strobe delay value using said final mapping comprises:

determining said final receive data strobe delay value at substantially a middle of a range of passing values of said final mapping.

16. The method of claim 13, further comprising storing a plurality of instructions for said writing, said performing, said comparing said measured data value to said expected value of said corresponding one of said plurality of data elements, said comparing said measured data value to said expected value of said corresponding next one of said plurality of data elements, and said determining in a basic input-output system (BIOS) memory.

17. The method of claim 13, further comprising:

for each of a plurality of transmit data delay values;

writing a second plurality of data elements in a burst cycle starting at said initial burst address over said memory interface for storage in said DRAM using a corresponding one of said plurality of transmit data delay values;

performing a second read burst cycle starting at said initial burst address over said memory interface using said final receive data strobe delay value to retrieve a second measured data value; and

comparing said second measured data value to an expected value of a corresponding one of said second plurality of data elements to provide a third comparison result, and

determining a final transmit data delay value using said third comparison result for each of said plurality of transmit data delay values to determine a final transmit data delay value.

18. The method of claim 13, further comprising:

initializing a working transmit data delay value to half of a unit

interval prior to said writing; and

changing said working transmit data delay value to progressively diverging values and repeating said writing, performing said read burst cycle, comparing said measured data value to said expected value of said corresponding one of said plurality of data elements, and comparing said measured data value to an expected value of a corresponding next one of said plurality of data elements until said first and second comparison results for one of said plurality of values of said receive data strobe delay pass.

19. The method of claim 18, wherein said changing said working transmit data delay value to progressively diverging values comprises alternatingly adding to and subtracting from said working transmit data delay value a value equal to a predetermined delay.

20. A method of training timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller comprises:

determining a left edge of passing receive enable delay values;

training a final value of a receive data strobe delay value and a final value of a transmit data delay value;

determining a right edge of passing receive enable delay values using a working value of said receive data strobe delay; and

setting a final receive enable delay value intermediate between said left edge of passing receive enable delay values and said right edge of passing receive enable delay values.

21. The method of claim 20, further comprising:

setting a working value of said receive enable delay based on said left edge, and

wherein said training comprises;

performing said training using said working value of said receive enable delay.

22. The method of claim 20, further comprising storing a plurality of instructions for

performing said determining said left edge, training, determining said right edge,

and setting in a basic input-output system (BIOS) memory.

23. The method of claim 20, further comprising:

setting said working receive data strobe delay value as a different value than said final receive data strobe delay value.