System and Method for Multi-Channel Control System

• US 20090245344A1
• Filed: 04/01/2008
• Published: 10/01/2009
• Est. Priority Date: 04/01/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG, Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Ploix, Olivier Dominique
• Granted Patent: US 8,634,941 B2
• Time in Patent Office: Days
• US Class Current: 375/238
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/21013 Microcontroller and power output switches integrated on same chip
• CPC Class Codes: G08C 19/22 by varying the duration of individual pulses
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H05B 45/37 Converter circuits
• CPC Class Codes: Y02B 20/30 Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

A system having has a pulse width modulation controller to successively activate each of a plurality of channels each in its own individual channel time slot is described. The system also has a sampling multiplexer configured to successively sample a signal derived from each of the plurality of channels during each individual channel time slot. Each individual time slot has an individual sampling sequence.

Claims

1. A multichannel control system comprising:

a pulse width modulation controller, wherein the controller is configured to successively activate each of a plurality of channels, each in its own individual channel time slot; and

a sampling multiplexer configured to successively sample a signal derived from each of the plurality of channels during each individual channel time slot, wherein each individual time slot comprises an individual sampling sequence.

2. The control system according to claim 1, wherein each individual sampling sequence samples each of the plurality of channels a fixed delay from the beginning of each individual channel time slot.

3. The control system according to claim 1, further comprising an Analog to Digital converter coupled to an output of the sampling multiplexer.

4. The control system according to claim 1, further comprising a bus interface coupled to the pulse width modulation controller and the sampling multiplexer.

5. The control system according to claim 4, wherein the bus interface comprises a Serial Peripheral Interface (SPI) Bus.

6. The control system according to claim 4, wherein the bus interface comprises a Local Interconnect (LIN) Bus, a Ccontroller Area Network (CAN) bus, or a FlexRay bus.

7. The control system according to claim 1, wherein each individual sampling sequence comprises a barrel shifted version of a same sequence in which the pulse width modulation controller successively activates each of the plurality of channels.

8. The control system according to claim 7, wherein the sampling sequence is barrel shifted such that a second element of each individual sampling sequence corresponds to a channel currently being activated by the pulse width modulation controller.

9. The control system according to claim 1, further comprising a lamp driver coupled to at least one of the plurality of output drivers.

10. The control system of claim 9, wherein the lamp driver comprises an LED driver.

11. The method of claim 9, wherein the sampling multiplexer is coupled to a current related to a current supplied by at least one of the plurality of output drivers.

12. A method of operating a multichannel control system, the system comprising:

activating an output on a first channel;

while activating the output on the first channel, sampling a signal derived from a channel other than the first channel; and

after sampling the signal derived from the channel other than the first channel, sampling a signal derived from the first channel.

13. The method of claim 12, further comprising:

converting the sampled signal from the first channel from an analog domain to a digital domain representation; and

writing the digital domain representation to a first channel A/D register.

14. The method of claim 13, further comprising:

writing a command on an interface bus to activate the first channel before activating the output on the first channel;

writing a command on the interface bus to read the first channel A/D register; and

reading the first channel A/D register on the interface bus.

15. The method of claim 14, further comprising reading the first channel A/D register for a last sample before the first channel is deactivated.

16. The method of claim 15, wherein:

activating the output on the first channel comprises illuminating a light;

writing a command on the interface bus to activate the first channel comprises writing a frequency and a pulse width;

the sampled signal from the first channel is a signal derived from a performance parameter of the light; and

the method further comprising adjusting the frequency and pulse width based on the contents of the first channel A/D register.

17. The method of claim 12, wherein writing a command on the interface bus to activate the first channel comprises writing a pulse width.

18. The method of claim 12, wherein activating the output on the first channel comprises illuminating a light.

19. The method of claim 12, further comprising activating an output on a second channel after sampling a signal derived from the first channel;

while activating the output on the second channel, resampling the signal derived from the first channel; and

after sampling the signal derived from the first channel, sampling a signal derived from the second channel.

20. The method of claim 19, further comprising:

successively activating outputs on additional channels;

sampling a signal derived from each additional channel a fixed period of time after each channel is activated;

converting the signal derived from each additional channel a fixed period of time after each channel is activated to a digital domain; and

writing the converted signal from each additional channel to a channel designated A/D register, wherein the channel designated A/D register is overwritten;

deactivating an output on a particular channel; and

holding the value of a A/D register of the particular channel after deactivating the output of the particular channel.

21. A semiconductor circuit for controlling a plurality of lights, the circuit comprising:

a pulse width modulator, the pulse width modulator configured to

provide a signal comprising a duty cycle and a frequency to a plurality of output channels, and

stagger the timing of each signal on the plurality of output channels so that none of the plurality of outputs transition simultaneously;

light sources coupled to ones of the plurality of output channels;

feedback paths coupled to ones of the plurality of output channels;

an analog to digital converter configured to successively sample each of the plurality of feedback paths; and

a bus interface coupled to the pulse width modulator and the analog to digital converter.

22. The semiconductor circuit of claim 21, wherein:

each output channel is activated in a first repeating sequence of designated output channel time slots; and

the analog to digital converter successively samples each of the plurality of feedback paths in a second repeating sequence, the second repeating sequence comprising a shift of the first sequence, wherein a magnitude of the shift is depends on which one of the plurality of output channels is being activated.

23. The semiconductor circuit of claim 22, wherein the shift is configured cause a feedback channel coupled to the present channel to be sampled at a fixed number of second repeating sequence intervals from a beginning of a present channel time period.

24. The semiconductor circuit of claim 22, wherein the pulse width modulator is configured to output a plurality of output frequencies and a plurality of pulse widths.

25. A system for controlling a pulse width modulated peripheral device, the system comprising:

a pulse width modulator configured to provide a signal comprising a duty cycle and a frequency to a plurality of output channels, and stagger the timing of each signal on the plurality of output channels so that none of the plurality of outputs turn on simultaneously;

peripheral devices coupled to ones of the plurality of output channels;

feedback paths coupled to ones of the plurality of output channels;

an analog to digital converter configured to successively sample each of the plurality of feedback paths;

a bus interface coupled to the pulse width modulator and the analog to digital converter; and

a controller coupled to the bus interface, the controller configured to issue commands to the pulse with modulator.