PATTERNING RESOLUTION ENHANCEMENT COMBINING INTERFERENCE LITHOGRAPHY AND SELF-ALIGNED DOUBLE PATTERNING TECHNIQUES

• US 20090246706A1
• Filed: 04/01/2008
• Published: 10/01/2009
• Est. Priority Date: 04/01/2008
• Status: Abandoned Application

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: HENDEL, RUDOLF, Liu, Kuo-Shih, Rao, Zhilong
• Application Number:
  US12/060,612
• Publication Number:
  US 20090246706A1
• Time in Patent Office: Days
• US Class Current: 430/314
• CPC Class Codes: G03F 7/70408 Interferometric lithography; Holographic lithography; Self-imaging lithography, e.g. utilizing the Talbot effect
• CPC Class Codes: G03F 7/7045 Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask

Abstract

A method for providing regular line patterns using interference lithography and sidewall patterning techniques is provided according to one embodiment. The method comprising may include producing regularly spaced parallel lines on a template using interference lithography techniques and then depositing sidewalls on the longitudinal sides of the regularly spaced parallel lines using sidewall patterning techniques. Various deposition and etching steps may also be included. The embodiments of the invention may provide regular line patterns with a line density half the interference lithography line density. Various lithography techniques may also be used to crop rounded connecting resulting from the sidewall patterning and/or to alter portions of the line pattern.

Claims

1. A method for providing regular line patterns using interference lithography and sidewall patterning techniques, the method comprising:

providing a plurality of regularly spaced parallel lines on a template using interference lithography, wherein the template is provided on a substrate;

depositing sidewalls on at least both longitudinal sides of the plurality of regularly spaced parallel lines;

removing the plurality of regularly spaced parallel lines, wherein after removal of the plurality of regularly spaced parallel lines a plurality of sidewall lines are left on the substrate;

etching portions of the substrate; and

removing the sidewall lines.

2. The method according to claim 1, wherein the template is a hardmask.

3. The method according to claim 1, wherein the providing a plurality of regularly spaced parallel lines on a template using interference lithography further comprises:

exposing a plurality of regularly spaced parallel lines on a photoresist layer using interference lithography;

developing the photoresist layer to create a plurality of regularly spaced parallel lines in the photoresist;

trimming each of the plurality of regularly spaced parallel lines such that the ratio of line width to line spacing is about 33%;

etching the template to form a plurality of regularly spaced parallel lines in the template; and

removing the photoresist layer.

4. The method according to claim 1, further comprising cropping the plurality of sidewall lines.

5. The method according to claim 1, further comprising:

applying a positive-tone photoresist;

exposing portions of the photoresist covering sidewall lines using photolithography;

wherein the exposed portions of the photoresist-covered sidewall lines are configured to introduce features within at least one sidewall line; and

developing the photoresist and etch portions of sidewall lines using photoresist as etch mask, wherein the etching removes portions of the exposed sidewall lines.

6. The method according to claim 1, further comprising:

applying a negative-tone photoresist;

exposing portions of the photoresist-covered sidewall lines using photolithography;

wherein the exposed portions of the sidewall lines are configured to introduce features within at least one sidewall line; and

developing photoresist and etch portions of the sidewall lines using photoresist as etch mask, wherein the etching removes portions of the unexposed sidewall lines.

7. The method according to claim 1, wherein the plurality of regularly spaced parallel lines on the template have a half pitch including and in between 22 nm and 30 nm.

8. The method according to claim 1, wherein the plurality of sidewall lines have a half pitch including and in between 11 nm and 15 nm.

9. The method according to claim 1, wherein said interference lithography uses immersion techniques.

10. The method according to claim 1, wherein the sidewalls comprise a dielectric and the sidewalls are deposited using chemical vapor deposition.

11. The method according to claim 1, wherein the template comprises an amorphous carbon hardmask.

12. The method according to claim 1, wherein the template comprises an Advanced Patterning Film.

13. A method for providing printed line widths with a half pitch below 22 nm on a substrate, the method comprising:

providing a plurality of regularly spaced printed lines on a template with a half pitch below 44 nm using interference lithography techniques; and

applying spacers on the longitudinal sides of the plurality of printed lines on the template, wherein the spacers have a half pitch below 22 nm.

14. The method according to claim 13, further comprising:

removing the plurality of printed lines on the template;

applying a positive-tone photoresist onto the template and exposing the template using a photolithography mask, wherein the mask exposes rounded spacer connects formed at the lateral ends of the printed lines during spacer application;

developing the resist;

etching the spacers, wherein the etching removes the exposed portions of the spacers; and

removing portions of the substrate not covered by the template.

15. A method for providing an array of regularly spaced printed lines in a semiconductor device, the method comprising:

providing a semiconductor device, wherein the semiconductor device includes a plurality of layers including a substrate, hardmask and photoresist;

exposing a line pattern in the photoresist using interference lithography, wherein the line pattern has a first line width and a first line spacing;

developing the line pattern in the photoresist, wherein after the developing a photoresist line pattern is formed on the hardmask;

trimming the photoresist line pattern;

wherein the resulting trimmed line pattern has a second line width and a second line spacing, the second line spacing is equal to approximately three times the second line width, and the second line spacing is narrower than the first line spacing;

etching the hardmask, wherein after the etching a hardmask line pattern is formed in the hardmask;

removing the photoresist;

depositing a spacer film over at least the hardmask line pattern;

etching the spacer film, wherein after the etching a plurality of spacer lines are formed at the sidewalls of the hardmask line pattern, each of the spacer lines have a line width approximately equal to the second line width, the etching results in rounded spacer connects;

removing the hardmask;

cropping the rounded spacer connects; and

etching the substrate, wherein after the etching a plurality of lines are formed in the substrate.

16. The method according to claim 15, wherein the cropping utilizes a photolithography technique.

17. The method according to claim 15, further comprising introducing features in the spacer line pattern using a photolithography technique.

18. The method according to claim 15, further comprising introducing features in the spacer line pattern using E-beam techniques.

19. The method according to claim 15, wherein the cropping comprises:

applying a photoresist,

exposing the photoresist using a trim mask, wherein the trim mask is configured to aid in cropping at least the rounded spacer connects;

developing the photoresist; and

etching the spacers, wherein the etching removes at least the rounded spacers connects.

20. The method according to claim 19, wherein the trim mask is further configured to introduce features in the spacer line pattern.

21. The method according to claim 19, wherein the etching further introduces features in the spacer line pattern.

22. The method according to claim 19, further comprising ashing the photoresist.

23. The method according to claim 15, further comprising cropping the rounded spacer connects and introducing features in the spacer line pattern using the same photolithography process.

24. The method according to claim 15, wherein the photoresist line pattern has a line density of less than or equal to 30 nm half pitch.

25. The method according to claim 15, wherein the spacer line pattern has a line density of less than or equal to 15 nm half pitch.