Embedded Control System

• US 20090249040A1
• Filed: 02/19/2009
• Published: 10/01/2009
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Ohkawa, Keiichiro, FUJIMOTO, Shinya
• Granted Patent: US 8,484,266 B2
• Time in Patent Office: Days
• US Class Current: 712/222
• CPC Class Codes: G06F 1/035 Reduction of table size G06F1/0314 takes precedence
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence

Abstract

An embedded control system capable of ensuring precision in arithmetic with data in the floating-point format and also avoiding a shortage of the storage area of a memory is provided.

According to an embedded control system in the present invention, when discrete data in the floating-point format is stored in a read-only memory, the discrete data in the floating-point format is converted into data in a significand-reduced floating-point format before being stored. Here, a significand-reduced floating-point number is a number obtained by deleting low-order bits of the significand of a floating-point number. Further, an interpolation search is performed using discrete data, the discrete data in the significand-reduced floating-point format stored in the read-only memory is brought back to the discrete data in the floating-point format before an interpolation search being performed.

Claims

1. An embedded control system provided with a microcomputer having a read-only memory for storing data in a floating-point format and a central processing unit for performing arithmetic operations on the data in the floating-point format, wherein

when the central processing unit stores discrete data in the floating-point format in the read-only memory, the central processing unit converts discrete data in the floating-point format into data in a significand-reduced floating-point format in which low-order bits of the significand of data in the floating-point format are deleted before the discrete data being stored, and

when the central processing unit performs an interpolation search using the discrete data in the significand-reduced floating-point format stored in the read-only memory, the central processing unit performs an interpolation search after the discrete data in the significand-reduced floating-point format being converted into discrete data in the floating-point format.

2. The embedded control system according to claim 1, wherein the central processing unit appends a predetermined value to the deleted low-order bits of the significand when the discrete data in the significand-reduced floating-point format being converted into discrete data in the floating-point format.

3. The embedded control system according to claim 2, wherein the predetermined value is 0.

4. The embedded control system according to claim 2, wherein the predetermined value is a value substantially half a maximum value that can be taken by the predetermined value.

5. The embedded control system according to claim 1, wherein when the central processing unit converts the discrete data in the floating-point format into the discrete data in the significand-reduced floating-point format, if a highest-order bit of the deleted low-order bits of the data in the floating-point format is “

1”

, the central processing unit adds 1 to high-order bits of the significand of the data in the significand-reduced floating-point format.

6. The embedded control system according to claim 1, wherein the discrete data in the floating-point format is 4-byte data including a 1-bit sign bit, an 8-bit exponent part, and the 23-bit significand, and the discrete data in the significand-reduced floating-point format is 2-byte data including the 1-bit sign bit, the 8-bit exponent part, and the 16-bit significand and is obtained by deleting 16 low-order bits of the significand of the data in the floating-point format.

7. The embedded control system according to claim 1, wherein the discrete data in the significand-reduced floating-point format includes an identification bit indicating the number of bytes of the significand-reduced floating-point number.

8. The embedded control system according to claim 7, wherein the identification bit is arranged at the head of the discrete data in the significand-reduced floating-point format.

9. The embedded control system according to claim 1, wherein the discrete data in the floating-point format is 4-byte data including a 1-bit sign bit, an 8-bit exponent part, and the 23-bit significand and the discrete data in the significand-reduced floating-point format is 2-byte data including a 1-bit identification bit, the 1-bit sign bit, the 8-bit exponent part, and the 6-bit significand and is obtained by deleting 16 low-order bits of the significand of the data in the floating-point format.

10. The embedded control system according to claim 1, wherein the discrete data in the floating-point format is 4-byte data including a 1-bit sign bit, an 8-bit exponent part, and the 23-bit significand and the discrete data in the significand-reduced floating-point format is 3-byte data including a 1-bit identification bit, the 1-bit sign bit, the 8-bit exponent part, and the 14-bit significand and is obtained by deleting 8 low-order bits of the significand of the data in the floating-point format.

11. The embedded control system according to claim 1, further comprising a random access memory for temporarily storing data in the floating-point format and a backup memory for storing saved data identical to data temporarily stored in the random access memory, wherein

when the central processing unit stores data in the floating-point format stored in the random access memory in the backup memory, the central processing unit converts the data in the floating-point format into the data in the significand-reduced floating-point format before the data being stored.