APPARATUS AND METHOD FOR LOW OVERHEAD CORRELATION OF MULTI-PROCESSOR TRACE INFORMATION

• US 20090249046A1
• Filed: 03/31/2008
• Published: 10/01/2009
• Est. Priority Date: 03/31/2008
• Status: Abandoned Application

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: KINTER, Ryan C., BERG, Thomas Benjamin, PATWARDHAN, Jaidev Prasad, THEKKATH, Radhika
• Application Number:
  US12/060,214
• Publication Number:
  US 20090249046A1
• Time in Patent Office: Days
• US Class Current: 712/227
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 12/0815 Cache consistency protocols

Abstract

A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a coherence indicator that demarks selective shared memory transactions. Coherence manager trace information is generated for each of the processors. The coherence manager trace information for each processor includes trace metrics and a coherence indicator.

Claims

1. A method of coordinating trace information in a multiprocessor system, comprising:

receiving processor trace information from a plurality of processors, wherein the processor trace information from each processor includes a processor identity and a coherence indicator demarking selective shared memory transactions; and

generating coherence manager trace information for each of the plurality of processors, wherein coherence manager trace information for each processor includes trace metrics and a coherence indicator.

2. The method of claim 1 further comprising identifying a trace stream of processor trace information and coherence manager trace information for at least one specified processor of the plurality of processors.

3. The method of claim 2 further comprising processing the trace stream to analyze interactions between processors of the plurality of processors.

4. The method of claim 2 further comprising incrementing the coherence indicator value in response to a synchronization signal and a shared memory transaction.

5. The method of claim 2 further comprising incrementing the coherence indicator value in response to a synchronization signal and a coherence manager overflow signal.

6. A system, comprising:

a set of processors generating multi-processor trace information, each processor of the set of processors generating trace information and a coherence indicator for a set of transactions;

a coherence manager to generate multi-processor trace messages that include coherence indicators; and

a computer to

organize, in accordance with the coherence indicators, the multi-processor trace messages into different trace streams, and

debug the different trace streams.

7. The system of claim 6 wherein each processor generates a coherence indicator as a function of a processor synchronization signal and a shared memory miss signal.

8. The system of claim 6 wherein the coherence manager includes circuitry to generate coherence manager trace information for each of the plurality of processors, wherein coherence manager trace information for each processor includes trace metrics and a coherence indicator.

9. The system of claim 6 wherein the coherence indicator value is incremented in response to a synchronization signal and a shared memory transaction.

10. The system of claim 6 wherein the coherence indicator value is incremented in response to a synchronization signal and a coherence manager overflow signal.

11. A computer readable storage medium with executable instructions to characterize a processor, comprising executable instructions to define:

a trace generation block to generate trace information; and

a coherence block to generate a coherence indicator derived as a function of a processor synchronization signal and a shared memory miss signal.

12. The computer readable storage medium of claim 11 wherein the processor synchronization signal toggles in response to the start of a trace.

13. The computer readable storage medium of claim 11 wherein the processor synchronization signal toggles in response to an overflow.

14. The computer readable storage medium of claim 11 wherein the processor synchronization signal toggles on a synchronization period trigger.

15. The computer readable storage medium of claim 11 wherein the coherence indicator is a two bit value selectively incremented.

16. A computer readable storage medium with executable instructions to characterize a coherency manager, comprising executable instructions to define:

ports to receive processor trace information from a plurality of processors, wherein the processor trace information from each processor includes a processor identity and a coherence indicator demarking selective shared memory transactions; and

circuitry to generate coherence manager trace information for each of the plurality of processors, wherein coherence manager trace information for each processor includes trace metrics and the coherence indicator.

17. The computer readable storage medium of claim 16 wherein the coherence indicator is derived as a function of a processor synchronization signal and a memory miss signal.

18. The computer readable storage medium of claim 16 wherein the coherence indicator is derived as a function of a processor synchronization signal and a coherence manager overflow signal.

19. A computer readable storage medium with executable instructions to characterize a trace information controller, comprising executable instructions to define:

a serializer circuit to form serialized trace information derived from trace information from a plurality of processors;

a serialized request handler to provide global transaction ordering of the serialized trace information and to provide serialized request handler trace frames;

an intervention unit to send coherent requests to the plurality of processors, receive coherent responses from the plurality of processors, and generate intervention unit trace frames; and

a coherence manager trace control block to process the serialized request handler trace frames and intervention unit trace frames to produce trace words.

20. The computer readable storage medium of claim 19 wherein the serialized request handler routes requests to a memory interface, memory mapped input/output, and the intervention unit.

21. The computer readable storage medium of claim 19 wherein the serialized request handler and the intervention unit stop tracing in response to predefined state of the coherence manager trace control block.

22. The computer readable storage medium of claim 21 wherein the coherence manager trace control block includes a queue that is emptied when the serialized request handler and the intervention unit stop tracing.

23. The computer readable storage medium of claim 22 wherein the serialized request handler and the intervention unit re-initiate tracing in response to a resynchronization signal applied to all processors of the plurality of processors.

24. The computer readable storage medium of claim 22 wherein the trace information controller is configured to selectively trace transactions.

25. The computer readable storage medium of claim 22 wherein the trace information controller traces different amounts of information at different ports.

26. The computer readable storage medium of claim 22 wherein the serialized request handler and the intervention unit trace information is correlated.

27. The computer readable storage medium of claim 22 wherein the trace information controller is controlled by a probe.

28. The computer readable storage medium of claim 22 wherein the trace information controller is controlled by software executing on an individual processor of the plurality of processors.