FAULT DIAGNOSIS OF COMPRESSED TEST RESPONSES
First Claim
1. A computer-implemented method of diagnosing faults in a circuit-under-test comprising:
- receiving at least one error signature comprising multiple bits, the bits of the error signature corresponding to bits of a compressed test response produced by a compactor in the circuit-under-test in response to at least one applied test pattern, the bits of the error signature further comprising one or more error bits that indicate errors at corresponding one or more bit locations of the compressed test response;
evaluating plural potential-error-bit-explaining scan cell candidates using a search tree;
determining whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells; and
providing an output of any such determined one or more failing scan cells.
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Accused Products
Abstract
Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.
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Citations
21 Claims
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1. A computer-implemented method of diagnosing faults in a circuit-under-test comprising:
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receiving at least one error signature comprising multiple bits, the bits of the error signature corresponding to bits of a compressed test response produced by a compactor in the circuit-under-test in response to at least one applied test pattern, the bits of the error signature further comprising one or more error bits that indicate errors at corresponding one or more bit locations of the compressed test response; evaluating plural potential-error-bit-explaining scan cell candidates using a search tree; determining whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells; and providing an output of any such determined one or more failing scan cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A computer-implemented method of diagnosing faults in a circuit-under-test comprising:
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receiving an error signature comprising multiple bits, the bits of the error signature corresponding to bits of a compressed test response produced by a compactor in the circuit-under-test, the bits of the error signature further comprising one or more error bits that indicate errors at corresponding bit locations of the compressed test response; selecting at least one error bit of the error signature; selecting at least one scan cell candidate from a set of scan cells known to contribute to the bit of the compressed test response corresponding to the selected at least one error bit; and determining whether the selected at least one scan cell candidate explains the selected at least one error bit in the error signature by updating the error signature to include the contribution of the at least one selected error bit. - View Dependent Claims (18, 19, 20)
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21-32. -32. (canceled)
Specification