RAIL-TO-RAIL OPERATIONAL AMPLIFIER

• US 20090251214A1
• Filed: 04/01/2009
• Published: 10/08/2009
• Est. Priority Date: 04/02/2008
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Spectra Linear, Inc. (Silicon Laboratories Incorporated)
• Inventors: Shkidt, Alexei, Orberk, Omer Fatih
• Granted Patent: US 7,863,981 B2
• Time in Patent Office: Days
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45354 the AAC comprising offset means
• CPC Class Codes: H03F 2203/45512 the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45224 Complementary Pl types having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/45632 in differential amplifiers with FET transistors as the active amplifying circuit H03F3/4578 takes precedence

Abstract

A rail-to-rail operational amplifier has a pair of input terminals and an output terminal, and includes first and second parallel-connected differential input stages configured to generate a differential output signal OUTN, OUTP in response to a differential input signal VINN, VINP received at the pair of input terminals. Each of the first and second differential input stages in turn includes a pair of source-follower transistors and a pair of bulk-driven transistors. The pair of source-follower transistors are respectively coupled between the pair of input terminals and a bulk terminal of the pair of bulk-driven input transistors. Further, the pair of source-follower transistors in the first differential input stage have a different threshold voltage than the source-follower transistors in the second differential input stage.

Claims

1. An operational amplifier, comprising:

a first input module, comprising a first pair of input transistors and a first pair of output transistors, each of the first pair of input transistors having a first threshold voltage;

a second input module, comprising a second pair of input transistors and a second pair of output transistors, each of the second pair of input transistors having a second threshold voltage, the second threshold voltage being lower than the first threshold voltage,

wherein each of the first pair of output transistors has a bulk in communication with a respective one of the first pair of input transistors, and each of the second pair of output transistors has a bulk in communication with a respective one of the second pair of input transistors, and each input module is configured to;

receive a pair of input signals differentially at a pair of input nodes in communication with the first pair of input transistors and the second pair of input transistors;

use each pair of input transistors to generate a respective pair of bulk levels as a function of the pair of input signals;

control the bulks of each pair of output transistors as a function of the respective pair of bulk levels; and

use each pair of output transistors to generate a respective pair of output signals at a pair of output nodes as a function of the respective pair of bulk levels and at least one reference level, the pair of output nodes being in communication with the first pair of output transistors and the second pair of output transistors; and

a protection module, in communication with the first input module, and configured to generate a protection control signal as a function of at least one of the pair of input signals, wherein each of the pair of output signals generated by the first pair of output transistors has an amplitude that is at least partially controlled as a function of the protection control signal.

2. The operational amplifier of claim 1, wherein:

the first pair of input transistors includes enhancement-mode NMOS transistors; and

the second pair of input transistors includes native NMOS transistors.

3. The operational amplifier of claim 1, wherein:

the first pair of input transistors includes enhancement-mode NMOS transistors; and

the second pair of input transistors includes depletion-mode NMOS transistors.

4. The operational amplifier of claim 1, wherein:

the first pair of input transistors and the second pair of input transistors include NMOS transistors; and

the first pair of output transistors and the second pair of output transistors include PMOS transistors.

5. The operational amplifier of claim 4, wherein:

the first pair of output transistors manifest a parasitic bipolar effect when a common mode input level is below a threshold level, the common mode input level being defined as half the magnitude of the sum of the pair of input signals; and

the protection module is configured to at least partially compensate for the parasitic bipolar effect.

6. The operational amplifier of claim 4, wherein:

each of the first pair of input transistors has a drain, a source, and a gate;

the drain of each of the first pair of input transistors is coupled with a source voltage terminal;

the source of a first one of the first pair of input transistors is coupled with the bulk of a first one of the first pair of output transistors;

the source of a second one of the first pair of input transistors is coupled with the bulk of a second one of the first pair of output transistors;

the gate of the first one of the first pair of input transistors is coupled with a first one of the pair of input nodes;

the gate of the second one of the first pair of input transistors is coupled with a second one of the pair of input nodes; and

a drain of each of the first pair of output transistors is coupled with one of the pair of output nodes.

7. The operational amplifier of claim 6, wherein the protection module comprises:

a protection input transistor having a drain coupled with a source voltage terminal, a source coupled with the bulk of a protection output transistor, and a gate coupled with one of the pair of input signals,

wherein a drain of the protection output transistor is coupled with the source of each of the first pair of output transistors.

8. The operational amplifier of claim 1, wherein:

the first pair of input transistors is optimized to operate over a first common mode range defined by a range between a first lower limit and an first upper limit, the first lower limit being defined as a function of the first threshold voltage; and

the second pair of input transistors is optimized to operate over a second common mode range defined by a range between a second lower limit and an second upper limit, the second lower limit being defined as a function of the second threshold voltage,

wherein the second lower limit is lower than the first lower limit.

9. The operational amplifier of claim 8, wherein the protection module comprises:

a threshold generator, configured to define a protection control threshold as a function of the lower limit of the first common mode range; and

a protection control signal controller, configured to;

detect a common mode input level, wherein the common mode input level is defined as half the magnitude of the sum of the pair of input signals; and

when the common mode input level exceeds the protection control threshold, control the protection control signal to be substantially at a zero level.

10. The operational amplifier of claim 9, wherein the protection control signal controller is further configured to:

when the common mode input level falls below the protection control threshold, control the protection control signal to decrease a magnitude of the first pair of output signals.

11. The operational amplifier of claim 1, further comprising:

an output module, configured to generate an amplifier output signal as a function of the first pair of output signals and the second pair of output signals.

12. The operational amplifier of claim 11, wherein the output module comprises:

a summing module, configured to generate a single-ended output signal as a function of summing the first pair of output signals and the second pair of output signals.

13. The operational amplifier of claim 12, wherein the summing module comprises a folded cascode topology.

14. The operational amplifier of claim 11, wherein the output module further comprises:

an output gain module, configured to generate the amplifier output signal at least by applying gain to the single-ended output signal.

15. The operational amplifier of claim 14, wherein the output gain module comprises a capacitive load configured to increase output stabilization in a closed-loop configuration.

16. The operational amplifier of claim 1, further comprising:

a reference generator module, configured to generate the at least one reference level.

17. The operational amplifier of claim 1, further comprising:

a housing, configured to house at least the first input module, the second input module, and the protection module, and comprising a set of interface locations configured to provide external interfaces with at least the pair of input nodes.

18. A method for providing operational amplifier functionality, comprising:

receiving a pair of input signals differentially at a first pair of input devices, the first pair of input devices being optimized to operate over a first common mode range and configured to control bulks of a first respective pair of output devices;

receiving the pair of input signals differentially at a second pair of input devices, the second pair of input devices being optimized to operate over a second common mode range and configured to control bulks of a second respective pair of output devices, the second common mode range being different from the first common mode range;

using each pair of input devices to generate bulk levels at the bulks of each respective pair of output devices as a function of the pair of input signals;

generating a protection control signal as a function of at least one of the pair of input signals;

using the first respective pair of output devices to generate a first pair of output signals as a function of the bulk levels at the bulks of the first respective pair of output devices and the protection control signal; and

using the second respective pair of output devices to generate a second pair of output signals as a function of the bulk levels at the bulks of the second respective pair of output devices.

19. The method of claim 18, further comprising:

generating a set of reference signals, wherein the protection control signal, the first pair of output signals, and the second pair of output signals are generated partially as a function of the reference signals.

20. The method of claim 18, wherein:

each common mode range is defined by a range between a lower limit and an upper limit, and the lower limit of the first common mode range is greater than the lower limit of the second common mode range.

21. The method of claim 20, further comprising:

defining a protection control threshold as a function of the lower limit of the first common mode range; and

when a common mode input level exceeds the protection control threshold, controlling the protection control signal to be substantially at a zero level,

wherein the common mode input level is defined as half the magnitude of the sum of the pair of input signals.

22. The method of claim 21, further comprising:

when the common mode input level falls below the protection control threshold, controlling the protection control signal to decrease a magnitude of the first pair of output signals.

23. The method of claim 18, further comprising:

generating a single-ended output signal as a function of summing the first pair of output signals and the second pair of output signals.

24. The method of claim 23, further comprising:

generating an amplifier output signal by applying gain to the single-ended output signal.

25. The method of claim 24, further comprising:

coupling the amplifier output signal with one of the pair of input signals to create closed-loop feedback.

26. A system for providing operational amplifier functionality, comprising:

a first means for differentially receiving a pair of input signals, the first means being optimized to operate over a first common mode range and configured to generate a first bulk level and a second bulk level as a function of each of the pair of input signals, respectively;

a second means for differentially receiving the pair of input signals, the second means being optimized to operate over a second common mode range and configured to generate a third bulk level and a fourth bulk level as a function of each of the pair of input signals, respectively;

a third means for generating a protection control signal as a function of at least one of the pair of input signals;

a fourth means for generating a first output signal as a function of the first bulk level and the protection control signal;

a fifth means for generating a second output signal as a function of the second bulk level and the protection control signal;

a sixth means for generating a third output signal as a function of the third bulk level; and

a seventh means for generating a fourth output signal as a function of the fourth bulk level.

27. The system of claim 26, further comprising:

an eighth means for generating a single-ended output signal as a function of summing the first output signal, the second output signal, the third output signal, and the fourth output signal.

28. The system of claim 27, further comprising:

a ninth means for applying at least one output characteristic to the single-ended output signal to generate an amplifier output signal.

29. The system of claim 26, further comprising:

a tenth means for housing at least the first means, the second means, the fourth means, the fifth means, the sixth means, and the seventh means, the tenth means comprising an eleventh means for providing an interface between the first means and a source of the pair of input signals external to the tenth means.