AMPLIFIER OUTPUT STAGE WITH EXTENDED OPERATING RANGE AND REDUCED QUIESCENT CURRENT

• US 20090251215A1
• Filed: 04/07/2008
• Published: 10/08/2009
• Est. Priority Date: 04/07/2008
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Hughes, Rodney Alan
• Granted Patent: US 7,920,026 B2
• Time in Patent Office: Days
• US Class Current: 330/255
• CPC Class Codes: H03F 2203/45112 the biasing of the differential amplifier being controlled from the input or the output signal
• CPC Class Codes: H03F 2203/45292 the AAC comprising biasing means controlled by the signal
• CPC Class Codes: H03F 3/3066 the collectors of complementary power transistors being connected to the output
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier

Abstract

An output stage of an amplifier circuit includes one or more output transistors that are selectively driven by a boosted drive circuit, where the boosted drive circuit is arranged such that the output range of the amplifier circuit is increased while maintaining reduced quiescent current. The drive signal to each output transistor is selectively increased only when demanded by the output load conditions. The threshold for boosting the drive signal can be adjusted for optimized performance. In one example, a class AB output stage includes a separate drive boost circuit for each output transistor. For this example, each drive boost circuit has a separate threshold for boosting each of the drive signals to the output transistors. The boosting can also be adjusted to optimize the differential input stage and current mirror maximum current requirement while maintaining minimum required bias currents.

Claims

1. An output driver system that is responsive to a differential input signal to generate a drive current for an output transistor, wherein the output driver system is arranged to dynamically boost the drive current, the output driver system comprising:

a differential amplifier block that is arranged to generate a first current (I1) in response to the differential input signal, wherein the first current (I1) has a corresponding first magnitude corresponding to the sum (I+S), wherein I corresponds to a DC current portion from the differential amplifier and S corresponds to a signal varying portion from the differential amplifier;

a first gain block that is arranged to generate a second current (I2) in response to the first current, wherein the second current (I2) has a corresponding second magnitude that is related to the first magnitude by a scaling factor;

a threshold detector block that is arranged to generate a control signal in response to a comparison between the first magnitude of the first current (I1) and a threshold level (TH);

a second gain block that is arranged to generate a third current (I3) that is responsive to the control signal, wherein the third current (I3) has a third magnitude, and wherein the second gain block is arranged such that the third current (I3) is approximately zero when the magnitude of the first current (I1) is below the threshold (TH), and also arranged such that the third current (I3) is non-zero when the magnitude of the first current (I1) is above the threshold (TH);

a bias current block that is arranged to generate a nominal biasing current (IB) for the output transistor;

a current mirror block that is arranged to generate a fourth current (I4) that is proportional to the difference (I−

S) according to the scaling factor; and

a summer block that is arranged to combine the nominal biasing current (IB), the second current (I2), the third current (I3) and the fourth current (I4) as a biasing current (IOUT) for output transistor, wherein the summer block is arranged such that IOUT=IB+I2+I3−

I4.

2. The output driver system of claim 1, wherein the scaling factor corresponds to W such that I2=W*(I+S), I4=W*(I−

S), and IOUT=IB+I3+2*W*S.

3. The output driver system of claim 1, further comprising:

a second differential amplifier block that is arranged to generate a fifth current (I5) in response to the differential input signal, wherein the first current (I5) has a corresponding fifth magnitude corresponding to the difference (I−

S);

a third gain block that is arranged to generate a sixth current (I6) in response to the fifth current, wherein the sixth current (I6) has a corresponding sixth magnitude that is related to the fifth magnitude by the scaling factor;

a second threshold detector block that is arranged to generate a second control signal in response to a comparison between the fifth magnitude of the fifth current (I5) and a second threshold level (TH2);

a fourth gain block that is arranged to generate a seventh current (I7) that is responsive to the second control signal, wherein the seventh current (I7) has a seventh magnitude, and wherein the fourth gain block is arranged such that the seventh current (I7) is approximately zero when the magnitude of the fifth current (I5) is below the second threshold (TH2), and also arranged such that the seventh current (I7) is non-zero when the magnitude of the fifth current (I5) is above the second threshold (TH2);

a second bias current block that is arranged to generate a second nominal biasing current (IB2) for another output transistor;

a second current mirror block that is arranged to generate an eighth current (I8) that is proportional to the sum (I+S) according to the scaling factor; and

a second summer block that is arranged to combine the second nominal biasing current (IB2), the sixth current (I6), the seventh current (I7) and the eighth current (I8) as a second biasing current (IOUT2) for the another output transistor, wherein the second summer block is arranged such that IOUT2=IB2+I6+I7−

I8.

4. The output driver system of claim 3, wherein the scaling factor corresponds to W such that I6=W*(I−

S), I8=W*(I+S), and IOUT=IB+I3−

2*W*S.

5. An output driver circuit that is responsive to a differential input signal to generate a drive current for first and second output transistors, wherein the output driver circuit is arranged to dynamically boost the drive currents, the output driver circuit comprising:

a first current mirror circuit that includes a power terminal coupled to a first node, a first output coupled to a second node, a second output coupled to a third node, and a sense terminal coupled to a fourth node, wherein the first output of the first current mirror is arranged to provide a first current (IQ1) that is scaled according to a scaling factor (SF) relative to a third current (IQ3) sensed at the fourth node, wherein the second output of the first current mirror is arranged to provide a second current (IQ2) that is matched to the third current (IQ3);

a first amplifier circuit that includes a positive power terminal coupled to the second node, a negative power terminal coupled to a ninth node, an input terminal coupled to a seventh node, and an output terminal coupled to a fifth node, wherein a first portion of the differential input signal is coupled to the seventh node, wherein the first amplifier circuit has a DC biasing current corresponding to I;

a second amplifier circuit that includes a positive power terminal coupled to the fourth node, a negative power terminal coupled to a tenth node, an input terminal coupled to an eighth node, and an output terminal coupled to a sixth node, wherein a second portion of the differential input signal is coupled to the eighth node, wherein the second amplifier circuit has a DC biasing current also corresponding to I;

a resistor circuit that is coupled between the fifth node and the sixth node, wherein the resistor circuit is arranged to cooperate with the first amplifier circuit and the second amplifier circuit such that a current (S) flows through the resistor that corresponds to a signal varying portion from the first and second amplifier circuits;

a second current mirror circuit that includes a power terminal coupled to a twelfth node, a first output coupled to the ninth node, a second output coupled to an eleventh node, and a sense terminal coupled to the tenth node, wherein the first output of the second current mirror is arranged to provide a fourth current (IQ4) that is scaled according to the scaling factor (SF) relative to a sixth current (IQ6) sensed at the tenth node, wherein the second output of the second current mirror is arranged to provide a fifth current (IQ5) that is matched to the sixth current (IQ6);

a first drive circuit (X1) that includes a first current terminal coupled to the second node, a second current terminal coupled to the eleventh node, and a third current terminal coupled to a thirteenth node, wherein the thirteenth node is coupled to a first control terminal of the first output transistor, and wherein the first drive circuit is arranged to drive the first control terminal with a first output current (IB7) that corresponds to;

IB7=IBP+SF*S+GP_(I+S), where IBP is a nominal biasing current for the first output transistor, and GP_(I+S) is a dynamically varied gain boost that is approximately zero for (I+S) below a first threshold (THP), and non-zero for (I+S) above the first threshold (THP); and

a second drive circuit (X2) that includes a first current terminal coupled to the ninth node, a second current terminal coupled to the third node, and a third current terminal coupled to a fourteenth node, wherein the fourteenth node is coupled to a second control terminal of the second output transistor, and wherein the second drive circuit (X2) is arranged to drive the second control terminal with a second output current (IB8) that corresponds to;

IB8=IBN−

SF*S+GN<sub>(I−

S)</sub>, where IBN is a nominal biasing current for the second output transistor, and GN<sub>(I−

S)</sub> is a dynamically varied gain boost that is approximately zero for (I−

S) below a second threshold (THN), and non-zero for (I−

S) above the second threshold (THN).

6. The output driver circuit of claim 5, wherein the scaling factor (SF) corresponds to two (2) such that IB7=IBP+4*S+GP_(I+S) and IB8=IBN−

4*S+GN_(I-S).

7. The output drive circuit of claim 5, wherein the first current-mirror circuit comprises:

a first bipolar junction transistor with an emitter coupled to the first node, a base coupled to the fourth node, and a collector coupled to the second node;

a second bipolar junction transistor with an emitter coupled to the first node, a base coupled to the fourth node, and a collector coupled to the third node; and

a third bipolar junction transistor with an emitter coupled to the first node, a base coupled to the fourth node, and a collector coupled to the fourth node.

8. The output drive circuit of claim 5, wherein the first current-mirror circuit comprises:

a first MOS transistor with a source coupled to the first node, a gate coupled to the fourth node, and a drain coupled to the second node;

a second MOS transistor with a source coupled to the first node, a gate coupled to the fourth node, and a drain coupled to the third node; and

a third MOS transistor with a source coupled to the first node, a gate coupled to the fourth node, and a drain coupled to the fourth node.

9. The output drive circuit of claim 5, wherein the second current-mirror circuit comprises:

a first bipolar junction transistor with an emitter coupled to the twelfth node, a base coupled to the tenth node, and a collector coupled to the ninth node;

a second bipolar junction transistor with an emitter coupled to the twelfth node, a base coupled to the tenth node, and a collector coupled to the eleventh node; and

a third bipolar junction transistor with an emitter coupled to the twelfth node, a base coupled to the tenth node, and a collector coupled to the tenth node.

10. The output drive circuit of claim 5, wherein the second current-mirror circuit comprises:

a first MOS transistor with a source coupled to the twelfth node, a gate coupled to the tenth node, and a drain coupled to the ninth node;

a second MOS transistor with a source coupled to the twelfth node, a gate coupled to the tenth node, and a drain coupled to the eleventh node; and

a third MOS transistor with a source coupled to the twelfth node, a gate coupled to the tenth node, and a drain coupled to the tenth node.

11. The output drive circuit of claim 5, wherein the first drive circuit comprises a first biasing circuit that is arranged to generate the first nominal biasing current at the thirteenth node, wherein the first biasing circuit comprises:

a current source coupled between a first intermediate node and the twelfth node;

a first bipolar junction transistor with an emitter coupled to a second intermediate node, a base coupled to the first intermediate node, and the collector coupled to the first intermediate node;

a second bipolar junction transistor with an emitter coupled to the thirteenth node, a base coupled to the first intermediate node, and the collector coupled to the twelfth node;

a third bipolar junction transistor with an emitter coupled to the first node, a base coupled to the second intermediate node, and the collector coupled to the second intermediate node; and

a fourth bipolar junction transistor with an emitter coupled to the first node, a base coupled to the second intermediate node, and the collector coupled to the thirteenth node.

12. The output driver circuit of claim 11, wherein the first bipolar junction transistor and the first output transistor are matched to one another according to a first ratioed scaling factor (M).

13. The output drive circuit of claim 5, wherein the second drive circuit comprises a second biasing circuit that is arranged to generate the second nominal biasing current for the fourteenth node, wherein the second biasing circuit comprises:

a current source coupled between a first node and a first intermediate node;

a first bipolar junction transistor with an emitter coupled to a second intermediate node, a base coupled to the first intermediate node, and the collector coupled to the first intermediate node;

a second bipolar junction transistor with an emitter coupled to the fourteenth node, a base coupled to the first intermediate node, and the collector coupled to the first node;

a third bipolar junction transistor with an emitter coupled to the twelfth node, a base coupled to the second intermediate node, and the collector coupled to the second intermediate node; and

a fourth bipolar junction transistor with an emitter coupled to the twelfth node, a base coupled to the second intermediate node, and the collector coupled to the fourteenth node.

14. The output driver circuit of claim 13, wherein the first bipolar junction transistor and the second output transistor are matched to one another according to a first ratioed scaling factor (N).

15. The output drive circuit of claim 5, wherein the first drive circuit (X1) comprises a threshold detector circuit that is arranged to selectively generate the dynamically varied gain boost GP_(I+S), the threshold detector circuit comprising:

a resistor that is coupled between the thirteenth node and the eleventh node; and

a transistor that includes a first terminal coupled to the thirteenth node, a second terminal coupled to the twelfth node, and a control terminal coupled to the eleventh node, wherein the transistor is selectively activated in response to a voltage across the resistor, and wherein the transistor comprises one of a bipolar junction transistor and a MOS transistor.

16. The output drive circuit of claim 5, wherein the second drive circuit (X2) comprises a threshold detector circuit that is arranged to selectively generate the dynamically varied gain boost GN_(I−

S), the threshold detector circuit comprising;

a resistor that is coupled between the fourteenth node and the third node; and

a transistor that includes a first terminal coupled to the first node, a second terminal coupled to the fourteenth node, and a control terminal coupled to the third node, wherein the transistor is selectively activated in response to a voltage across the resistor, and wherein the transistor comprises one of a bipolar junction transistor and a MOS transistor.

17. An output driver circuit that is responsive to a differential input signal to generate a drive current for a first and second output transistor, wherein the output driver circuit is arranged to dynamically boost the drive signals to the output transistors, the output driver circuit comprising:

a first amplifier circuit that includes a first positive power terminal arranged to conduct a first amplifier positive supply current (IA1P=I+S), a first negative power terminal arranged to conduct a first amplifier negative supply current (IA1N=I−

S), and a first input terminal arranged to receive a first portion of the differential input signal;

a second amplifier circuit that includes a second positive power terminal arranged to conduct a second amplifier positive supply current (IA2P=I−

S), a second negative power terminal arranged to conduct a second amplifier negative supply current (IA2N=I+S), and a second input terminal arranged to receive a second portion of the differential input signal;

a resistor circuit that is coupled between outputs of the first and second amplifier circuits, and arranged to conduct an output current corresponding to S, where S corresponds to a signal varying current for the first and second amplifier circuits, and where I corresponds to a DC biasing current for the first and second amplifier circuits;

a first drive circuit that is arranged for driving a first control signal (IB7) to a control terminal of the first output transistor, responsive to signals from the first positive power terminal and a first drive circuit input such that IB7=IBP+SF*S+GP_(I+S), where IBP is a nominal biasing signal for the first output transistor, and GP_(I+S) is a dynamically varied gain boost that is approximately zero for (I+S) below a first threshold (THP), and non-zero for (I+S) above the first threshold (THP);

a second drive circuit that is arranged for driving a second control signal (IB8) to a control terminal of the second output transistor, responsive to signals from the first negative power terminal and a second drive circuit input such that IB8=IBN−

SF*S+GN<sub>(I−

S)</sub>, where IBN is a nominal biasing current for the second output transistor, and GN<sub>(I−

S)</sub> is a dynamically varied gain boost that is approximately zero for (I−

S) below a second threshold (THN), and non-zero for (I−

S) above the second threshold (THN);

a first transistor with a first terminal coupled to a positive power supply node, a control terminal coupled to the second positive power terminal, and a second terminal coupled to a first positive power terminal, wherein the first transistor is arranged to generate a current corresponding to SF*(I−

S);

a second transistor with a first terminal coupled to a positive power supply node, a control terminal coupled to the second positive power terminal, and a second terminal coupled to the second drive circuit input, wherein the second transistor is arranged to generate a current corresponding to (I−

S);

a third transistor with a first terminal coupled to a positive power supply node, a control terminal coupled to the second positive power terminal, and a second terminal coupled to the second positive power terminal, wherein the third transistor is arranged to sense a current corresponding to (I−

S);

a fourth transistor with a first terminal coupled to a negative power supply node, a control terminal coupled to the second negative power terminal, and a second terminal coupled to the second negative power terminal, wherein the fourth transistor is arranged to generate a current corresponding to SF*(I+S);

a fifth transistor with a first terminal coupled to a negative power supply node, a control terminal coupled to the second negative power terminal, and a second terminal coupled to the first drive circuit input, wherein the fifth transistor is arranged to generate a current corresponding to (I+S); and

a sixth transistor with a first terminal coupled to a negative power supply node, a control terminal coupled to the second negative power terminal, and a second terminal coupled to the second negative power terminal, wherein the sixth transistor is arranged to sense a current corresponding to (I+S).

18. The output drive circuit of claim 17, wherein the first drive circuit (X1) comprises a threshold detector circuit that is arranged to selectively generate the dynamically varied gain boost GP_(I+S), the threshold detector circuit comprising:

a boost transistor that includes a first terminal coupled to the negative power supply node, a control terminal coupled to the first drive circuit input, and a second terminal coupled to the control terminal of the first output transistor; and

a sense resistor circuit that is coupled between the first drive circuit input and the control terminal of the first output transistor, wherein the sense resistor circuit is arranged to conduct a current corresponding to (I+S), and wherein the sense resistor circuit is arranged to selectively activate the boost transistor when a voltage across the sense resistor circuit exceeds a predetermined threshold.

19. The output drive circuit of claim 18, wherein the second drive circuit (X2) comprises a second threshold detector circuit that is arranged to selectively generate the dynamically varied gain boost GN_(I−

S), the threshold detector circuit comprising;

a second boost transistor that includes a first terminal coupled to the positive power supply node, a control terminal coupled to the second drive circuit input, and a second terminal coupled to the control terminal of the second output transistor; and

a second sense resistor circuit that is coupled between the second drive circuit input and the control terminal of the second output transistor, wherein the second sense resistor circuit is arranged to conduct a current corresponding to (I−

S), and wherein the second sense resistor circuit is arranged to selectively activate the second boost transistor when a voltage across the second sense resistor circuit exceeds a second predetermined threshold.

20. The output driver circuit of claim 17, wherein the first output transistor is scaled relative to a first biasing transistor in the first drive circuit, and wherein the second output transistor is scaled relative to a second biasing transistor in the second drive circuit.