Semiconductor Device
First Claim
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1. A semiconductor device comprising:
- a first control circuit;
a second control circuit;
a transistor, the transistor being a p-type, a gate of the transistor being electrically connected to the first control circuit through a first word line, and one of a source and a drain of the transistor being electrically connected to the second control circuit through a bit line, anda memory element, a first terminal of the memory element being electrically connected to the other of the source and the drain of the transistor, and a second terminal of the memory element being electrically connected to the first control circuit through a second word line,wherein;
the first control circuit is configured to supply a first potential to the gate of the transistor through the first word line,the second control circuit is configured to supply a second potential to the one of the source and the drain of the transistor through the bit line,the first control circuit is configured to supply a third potential to the second terminal of the memory element through the second word line,the third potential at a time of data writing is negative potential, anda potential difference between the second potential and the third potential at the time of data wiring is larger than a withstand voltage of the transistor.
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Accused Products
Abstract
A semiconductor device is provided, which includes a transistor, a memory element, a first control circuit and a second control circuit. A gate of the transistor is electrically connected to the first control circuit through a first word line, one of a source and a drain of the transistor is electrically connected to the second control circuit through a bit line, the other of the source and the drain of the transistor is electrically connected to a first terminal of the memory element, and a second terminal of the memory element is electrically connected to the first control circuit through a second word line.
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Citations
18 Claims
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1. A semiconductor device comprising:
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a first control circuit; a second control circuit; a transistor, the transistor being a p-type, a gate of the transistor being electrically connected to the first control circuit through a first word line, and one of a source and a drain of the transistor being electrically connected to the second control circuit through a bit line, and a memory element, a first terminal of the memory element being electrically connected to the other of the source and the drain of the transistor, and a second terminal of the memory element being electrically connected to the first control circuit through a second word line, wherein; the first control circuit is configured to supply a first potential to the gate of the transistor through the first word line, the second control circuit is configured to supply a second potential to the one of the source and the drain of the transistor through the bit line, the first control circuit is configured to supply a third potential to the second terminal of the memory element through the second word line, the third potential at a time of data writing is negative potential, and a potential difference between the second potential and the third potential at the time of data wiring is larger than a withstand voltage of the transistor. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor device comprising:
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a first control circuit; a second control circuit; a transistor, the transistor being a p-type, a gate of the transistor being electrically connected to the first control circuit through a first word line, and one of a source and a drain of the transistor being electrically connected to the second control circuit through a bit line, and a memory element, a first terminal of the memory element being electrically connected to the other of the source and the drain of the transistor, and a second terminal of the memory element being electrically connected to the first control circuit through a second word line, wherein; the first control circuit is configured to supply a first potential to the gate of the transistor through the first word line, the second control circuit is configured to supply a second potential to the one of the source and the drain of the transistor through the bit line, the first control circuit is configured to supply a third potential to the second terminal of the memory element through the second word line, the third potential at a time of data writing is negative potential, a potential difference between the second potential and the third potential at the time of data wiring is larger than a withstand voltage of the transistor, and a potential difference between the first potential and the second potential at the time of data wiring is equal to or smaller than the withstand voltage of the transistor. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A semiconductor device comprising:
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a first control circuit; a second control circuit; a transistor, the transistor being a p-type, a gate of the transistor being electrically connected to the first control circuit through a first word line, and one of a source and a drain of the transistor being electrically connected to the second control circuit through a bit line, and a memory element, a first terminal of the memory element being electrically connected to the other of the source and the drain of the transistor, and a second terminal of the memory element being electrically connected to the first control circuit through a second word line, wherein; the first control circuit is configured to supply a first potential to the gate of the transistor through the first word line, the second control circuit is configured to supply a second potential to the one of the source and the drain of the transistor through the bit line, the first control circuit is configured to supply a third potential to the second terminal of the memory element through the second word line, the third potential at a time of data writing is negative potential, a potential difference between the second potential and the third potential at the time of data wiring is larger than a withstand voltage of the transistor, a potential difference between the first potential and the second potential at the time of data wiring is equal to or smaller than the withstand voltage of the transistor, and a potential difference between the first terminal of the memory element and the second terminal of the memory element at the time of data wiring is higher than the withstand voltage of the transistor. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsSaito, Toshihiko
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current365/72
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CPC Class CodesG11C 13/0004 comprising amorphous/crysta...G11C 13/0014 comprising cells based on o...G11C 13/003 Cell accessG11C 13/0069 Writing or programming circ...G11C 2013/0071 Write using write potential...G11C 2013/009 Write using potential diffe...G11C 2213/76 Array using an access devic...G11C 2213/79 Array wherein the access de...
