METHOD OF PROCESSING A SEMICONDUCTOR SUBSTRATE BY THERMAL ACTIVATION OF LIGHT ELEMENTS

• US 20090253225A1
• Filed: 03/10/2009
• Published: 10/08/2009
• Est. Priority Date: 04/03/2008
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: Dubois, Sebastien, Enjalbert, Nicolas, Monna, Remi
• Granted Patent: US 7,670,966 B2
• Time in Patent Office: Days
• US Class Current: 438/58
• CPC Class Codes: C30B 29/52 Alloys
• CPC Class Codes: C30B 33/02 Heat treatment C30B33/04, C30B33/06 take precedence
• CPC Class Codes: H01L 21/3225 Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering H01L21/3226 takes precedence
• CPC Class Codes: H01L 21/3242 for the formation of PN junctions without addition of impurities H01L21/22 takes precedence
• CPC Class Codes: H01L 31/03685 including microcrystalline silicon, uc-Si
• CPC Class Codes: H01L 31/1812 including only AIVBIV alloys, e.g. SiGe
• CPC Class Codes: H01L 31/182 Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
• CPC Class Codes: H01L 31/1864 Annealing
• CPC Class Codes: Y02E 10/546 Polycrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Method of processing a substrate containing at least one semiconductor of the Si_XA_Y type and comprising at least four separate types of light elements, comprising at least the following steps:

• • carrying out a first anneal of the substrate at a temperature T1 corresponding to a thermal activation temperature for a first one of the four types of light elements,
  • carrying out a second anneal of the substrate at a temperature T2 corresponding to a thermal activation temperature for a second one of the four types of light elements,
  • carrying out a third anneal of the substrate at a temperature T3 corresponding to a thermal activation temperature for a third one of the four types of light elements,
  • carrying out a fourth anneal of the substrate at a temperature T4 corresponding to a thermal activation temperature for a fourth one of the four types of light elements,
  • each anneal comprising a holding at the temperature T1, T2, T3 or T4 and the temperatures T1, T2, T3 and T4 being such that T1>T2>T3>T4.

Claims

1. Method of processing a substrate containing at least one semiconductor of the Si_XA_Y type, x being a strictly positive number, y being a positive number and A designating a chemical element or a compound of several chemical elements of the fourteenth column of the periodic table of elements, and comprising at least four separate types of light elements, the method comprising at least the following steps:

carrying out a first anneal of the substrate at a temperature T1, corresponding to a thermal activation temperature for a first one of the four types of light elements,

carrying out, after the first anneal, a second anneal of the substrate at a temperature T2, corresponding to a thermal activation temperature for a second one of the four types of light elements,

carrying out, after the second anneal, a third anneal of the substrate at a temperature T3, corresponding to a thermal activation temperature for a third one of the four types of light elements,

carrying out, after the third anneal, a fourth anneal of the substrate at a temperature T4, corresponding to a thermal activation temperature for a fourth one of the four types of light elements,

each anneal comprising a holding at the temperature T1, T2, T3 or T4 for a predetermined time period, and the temperatures T1, T2, T3 and T4 being such that T1>

T2>

T3>

T4.

2. Method according to claim 1, wherein the semiconductor is a p-type crystalline silicon.

3. Method according to claim 1, wherein each of the four types of light elements present in the semiconductor is either oxygen, nitrogen, carbon, hydrogen, fluoride, sulphur, chloride, a compound of nitrogen and oxygen, or other compounds of these various elements.

4. Method according to claim 1, wherein T1 is between approximately 530°

C. and approximately 830°

C., and/or T2 is between approximately 450°

C. and 750°

C., and/or T3 is between approximately 350°

C. and 650°

C., and/or T4 is between approximately 300°

C. and 600°

C.

5. Method according to claim 1, wherein T1 is equal to approximately 680°

C., and/or T2 is equal to approximately 600°

C., and/or T3 is equal to approximately 500°

C., and/or T4 is equal to approximately 450°

C.

6. Method according to claim 1, further comprising, after carrying out the fourth anneal, carrying out a fifth anneal at a temperature T5, corresponding to a thermal activation temperature for a fifth type of light elements present in the semiconductor, which is separate from the other four types of light elements present in the semiconductor, with T5<

T4.

7. Method according to claim 6, further comprising, after carrying out the fifth anneal, carrying out a sixth anneal at a temperature T6, corresponding to a thermal activation temperature for a sixth type of light elements present in the semiconductor, which is separate from the other five types of light elements present in the semiconductor, with T6<

T5.

8. Method according to claim 7, further comprising, after carrying out the sixth anneal, carrying out a seventh anneal at a temperature T7, corresponding to a thermal activation temperature for a seventh type of light elements present in the semiconductor, which is separate from the other six types of light elements present in the semiconductor, with T7<

T6.

9. Method according to claim 8, further comprising, after carrying out the seventh anneal, carrying out an eighth anneal at a temperature T8, corresponding to a thermal activation temperature for an eighth type of light elements present in the semiconductor, which is separate from the other seven types of light elements present in the semiconductor, with T8<

T7.

10. Method according to claim 1, wherein at least one of the annealing operations is carried out in a lamp oven in which the semiconductor-based substrate is arranged.

11. Method according to claim 1, wherein at least one of the annealing operations is carried out under an oxygen and/or nitrogen and/or hydrogen and/or argon and/or helium atmosphere.

12. Method according to claim 1, wherein the annealing operations are carried out on an ingot of the semiconductor, the substrate next being obtainable by cutting out a wafer from the ingot.

13. Method of producing a semiconductor substrate device from a substrate containing at least one semiconductor of the Si_XA_Y type, x being a strictly positive number, y being a positive number and A designating a chemical element or a compound of several chemical elements of the fourteenth column of the periodic table of elements, and comprising at least four separate types of light elements, comprising at least the implementation of the substrate processing method according to claim 1.

14. Method according to claim 13, wherein the semiconductor device comprises at least one photovoltaic cell.

15. Method according to claim 14, wherein the substrate contains p-type crystalline silicon, the method of producing the semiconductor device further comprising the following steps:

texturing at least a first face of the substrate intended to form a front face of the photovoltaic cell,

formation of an N+ doped layer at the faces of the substrate,

deposition of a passivation and/or anti-reflective layer on the N+ doped layer, at the level of the first face of the substrate,

producing conductive contacts on the passivation and/or anti-reflective layer and on the N+ doped layer, at the level of the second face, opposite the first face of the substrate,

annealing the conductive contacts,

etching the N+ doped layer at the level of the faces of the substrate which hare substantially perpendicular to the first and second faces of the substrate,

the steps of the substrate processing method being implemented prior to the texturing step, and/or after the etching step, and/or between two steps of the method of producing the semiconductor device.

16. Method according to claim 14, the substrate containing a p-type crystalline silicon, the method of producing the semiconductor device further comprising at least one step of depositing a layer of amorphous silicon onto two opposite faces of the substrate intended to form the front and rear faces of the photovoltaic cell, the steps of the substrate processing method being implemented prior to this deposition step.