MEMORY WITH EMBEDDED ASSOCIATIVE SECTION FOR COMPUTATIONS

• US 20090254697A1
• Filed: 05/12/2008
• Published: 10/08/2009
• Est. Priority Date: 04/02/2008
• Status: Abandoned Application

• Current Assignee: GSI Technology Incorporated
• Original Assignee: ZikBit Ltd
• Inventors: Lavi, Yoav, Akerib, Avidan, Meyassed, Moshe, Ehrman, Eli
• Application Number:
  US12/119,197
• Publication Number:
  US 20090254697A1
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.

Claims

1. An integrated circuit device comprising:

a semiconductor substrate;

an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data; and

a computational section comprising associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.

2. The device according to claim 1, wherein the RAM cells comprise dynamic RAM (DRAM) cells.

3. The device according to claim 1, wherein the computational section is configured to return a result of the associative computation to the array of the RAM cells.

4. The device according to claim 3, and comprising control logic, which is coupled to receive a command from a host processor invoking the associative computation, and to issue, responsively to the command, a sequence of micro-commands that cause the computational section to perform the associative computation, and to return the result to the array of the RAM cells.

5. The device according to claim 1, and comprising control logic, which is configured to accept first commands from a host processor specifying addresses for reading and writing of the data in the array of the RAM cells, and to accept second commands, which cause the computational section to perform the associative computation on the data.

6. The device according to claim 5, wherein the second commands are memory-mapped to the addresses in the array of the RAM cells.

7. The device according to claim 1, wherein the first columns comprise first bit lines, each first column comprising a respective first bit line coupled to the RAM cells in the first column and a respective sense amplifier coupled to the first bit line, and wherein each second column comprises a respective second bit line, which is coupled to the respective sense amplifier of at least one of the first columns.

8. The device according to claim 7, wherein the RAM cells and associative memory cells are arranged in respective first and second rows, and wherein the sense amplifiers are configured to transfer the data simultaneously via the bit lines between the RAM cells in one of the first rows and all of the associative memory cells in one of the second rows.

9. The device according to claim 1, wherein the first columns are mutually spaced by a predetermined first pitch, and wherein the second columns are mutually spaced by a second pitch, which is equal to the first pitch.

10. The device according to claim 1, wherein each of the associative memory cells comprises a storage cell, for holding a data bit, and compare logic, for performing a comparison between the data bit and a respective bit value of a comparand, and wherein the second columns comprise respective tag cells, such that a tag cell in each second column is coupled to receive a result of the comparison from the compare logic and to write a new bit value to the storage cell of at least one of the associative memory cells in the second column responsively to the comparison.

11. The device according to claim 10, wherein the tag cells are coupled to transfer and receive data bits to and from the tag cells in neighboring columns, so as to apply a shift to the data.

12. The device according to claim 1, wherein the associative memory cells are arranged in multiple rows and columns, and

wherein the computational section comprises a comparand register, for holding a comparand, and is configured to make a comparison between the data held in each of the columns and the comparand, and to write data bits to one or more of the associative memory cells responsively to a result of the comparison.

13. The device according to claim 12, wherein the computational section comprises a mask register, for holding a mask, and is configured to limit the comparison to the rows that are indicated by the mask.

14. The device according to claim 12, wherein the computational section is configured to write the data bits, responsively to the result of the comparison, so as to shift the data bits along at least one of the rows of the associative memory cells.

15. The device according to claim 14, wherein the data stored in the array of the RAM cells comprise a sequence of data words, and wherein the computational section is configured to read, compare and shift the data bits in the data words so as to transpose the data words from a row-wise to a column-wise orientation.

16. The device according to claim 15, wherein the computational section is configured to apply a bitwise computation to the data bits in the transposed data words, and to retranspose the data words following the bitwise computation for output from the device.

17. The device according to claim 14, wherein the computational section is configured to perform a neighborhood operation on the data by processing the data bits held in a first row of the associative memory cells together with the data bits in at least one shifted replica of the first row that is held in at least a second row of the associative memory cells.

18. The device according to claim 12, wherein the computational section is configured to write the data bits to a set of the associative memory cells, selected responsively to the comparison, in one of the rows while leaving the data held in the remaining memory cells in the one of the rows unchanged.

19. A method for computing, comprising:

accepting and executing at least one command from a host processor to a memory device, the at least one command comprising a write command to store data at a specified address in an array of random access memory (RAM) cells formed on a semiconductor substrate in the memory device;

responsively to the at least one command, transferring the data into a computational section of the memory device, the computational section comprising associative memory cells, which are disposed on the semiconductor substrate in communication with the array of the RAM cells; and

performing an associative computation on the data in the computational section.

20. The method according to claim 19, wherein the at least one command comprises a second command from the host processor to the memory device, which causes the computational section to perform the associative computation on the data.

21. The method according to claim 20, wherein the second command is memory-mapped to the specified address in the array of the RAM cells.

22. The method according to claim 19, wherein the RAM cells comprise dynamic RAM (DRAM) cells.

23. The method according to claim 19, and comprising returning a result of the associative computation from the computational section to the array of the RAM cells.

24. The method according to claim 23, wherein performing the associative computation comprises receiving a command from a host processor invoking the associative computation, and issuing within the memory device, responsively to the command, a sequence of micro-commands that cause the computational section to perform the associative computation, and to return the result to the array of the RAM cells.

25. The method according to claim 19, wherein the RAM cells are arranged in the array in first columns, and wherein the associative memory cells are arranged in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns.

26. The method according to claim 25, wherein the first columns comprise first bit lines, each first column comprising a respective bit line coupled to the RAM cells in the first column and a respective sense amplifier coupled to the first bit line, and wherein each second column comprises a respective second bit line, which is coupled to the respective sense amplifier of at least one of the first columns.

27. The method according to claim 26, wherein the RAM cells and associative memory cells are arranged in respective first and second rows, and wherein transferring the data comprises conveying the data simultaneously via the bit lines between the RAM cells in one of the first rows and all of the associative memory cells in one of the second rows.

28. The method according to claim 25, wherein the first columns are mutually spaced by a predetermined first pitch, and wherein the second columns are mutually spaced by a second pitch, which is equal to the first pitch.

29. The method according to claim 25, wherein each of the associative memory cells comprises a storage cell, for holding a data bit, and compare logic, for performing a comparison between the data bit and a respective bit value of a comparand, and wherein the second columns comprise respective tag cells, and

wherein performing the associative computation comprises receiving in a tag cell in each second column a result of the comparison from the compare logic, and writing a new bit value from the tag cell to the storage cell of at least one of the associative memory cells in the second column responsively to the comparison.

30. The method according to claim 29, wherein performing the associative computation comprises transferring data bits between the tag cells in neighboring columns, so as to apply a shift to the data.

31. The method according to claim 19, wherein the associative memory cells are arranged in multiple rows and columns, and wherein the computational section comprises a comparand register, for holding a comparand, and

wherein performing the associative computation comprises making a comparison between the data held in each of the columns and the comparand, and writing data bits to one or more of the associative memory cells responsively to a result of the comparison.

32. The method according to claim 31, wherein the computational section comprises a mask register, for holding a mask, and wherein making the comparison comprises limiting the comparison to the rows that are indicated by the mask.

33. The method according to claim 31, wherein making the comparison comprises writing the data bits, responsively to the result of the comparison, so as to shift the data bits along at least one of the rows of the associative memory cells.

34. The method according to claim 33, wherein the data stored in the array of the RAM cells comprise a sequence of data words, and wherein performing the associative computation comprises reading, comparing and shift the data bits in the data words so as to transpose the data words from a row-wise to a column-wise orientation.

35. The method according to claim 34, wherein performing the associate computation comprises applying a bitwise computation to the data bits in the transposed data words, and retransposing the data words following the bitwise computation for output from the device.

36. The method according to claim 33, wherein performing the associative computation comprises carrying out a neighborhood operation on the data by processing the data bits held in a first row of the associative memory cells together with the data bits in at least one shifted replica of the first row that is held in at least a second row of the associative memory cells.

37. The method according to claim 31, wherein writing the data bits comprises writing bit values to a set of the associative memory cells, selected responsively to the comparison, in one of the rows while leaving the data held in the remaining memory cells in the one of the rows unchanged.

38. An integrated circuit device, comprising:

a semiconductor substrate;

an array of random access memory (RAM) cells, which are disposed on the substrate and are configured to store data;

a computational section comprising associative memory cells, which are disposed on the substrate in communication with the array of the RAM cells; and

control logic, which is configured to accept and execute first commands from a host processor specifying read and write operations to be performed on the data in the RAM cells, and to accept second commands from the host processor, which cause the computational section to perform associative computations on the data.

39. The device according to claim 38, wherein the control logic is configured to cause the computational section to selectively write data bits to a set of the memory cells in a row of the device while leaving the data held in the remaining memory cells in the row unchanged.

40. A method for computing, comprising:

providing a memory device comprising an array of random access memory (RAM) cells, which are disposed on a semiconductor substrate and are configured to store data, and comprising a computational section, which comprises associative memory cells, which are disposed on the substrate in communication with the array of the RAM cells;

in response to first commands from a host processor to the memory device, performing read and write operations on the data in the RAM cells; and

in response to second commands from the host processor to the memory device, performing associative computations on the data in the computational section.

41. The method according to claim 40, wherein performing the associative computations comprises selectively writing data bits to a set of the memory cells in a row of the device while leaving the data held in the remaining memory cells in the row unchanged.