BUS ATTACHED COMPRESSED RANDOM ACCESS MEMORY

• US 20090254705A1
• Filed: 04/07/2008
• Published: 10/08/2009
• Est. Priority Date: 04/07/2008
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lastras-Montano, Luis A., Karidis, John P., Abali, Bulent
• Application Number:
  US12/098,900
• Publication Number:
  US 20090254705A1
• Time in Patent Office: Days
• US Class Current: 711/117
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/2024 Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
• CPC Class Codes: G06F 2212/401 Compressed data

Abstract

A computer memory system having a three-level memory hierarchy structure is disclosed. The system includes a memory controller, a volatile memory, and a non-volatile memory. The volatile memory is divided into an uncompressed data region and a compressed data region.

Claims

1. A computer memory system having a multi-level hierarchical memory structure, the computer memory system comprising:

a first-type memory being a volatile memory and having a uncompressed data region (L3) and a compressed data region (L4);

a second-type memory (L5) being an non-volatile memory, being slower than the first-type memory, having more capacity than the first-type memory, and storing compressed data; and

a memory controller means for controlling a direct I/O access to the first-type memory and the second-type memory, for controlling data exchange between the first-type memory and the second-type memory (L5) in response to an issuance of a memory access request from a general purpose processor, and for controlling data exchange between the uncompressed data region (L3) and the compressed data region (L4) in the first-type memory according to an issuance of a memory accesses request from the general purpose processor.

2. The computer memory system according to claim 1, wherein

the first-type memory is one of:

Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM); and

the second-type memory is one of;

NAND-based flash memory, NOR-based flash memory, Phase Change Memory (PCM), Ferroelectric RAM (FeRAM), and Magnetoresistive RAM (MRAM).

3. The computer memory system according to claim 1, wherein a size of the compressed data region (L4) and a size of the uncompressed data region (L3) are fixed.

4. The computer memory system according to claim 1, wherein a size of the compressed data region (L4) and a size of the uncompressed data region (L3) are dynamically adjusted based on a compressibility of data in the first-type memory.

5. The computer memory system according to claim 1, wherein the uncompressed data region (L3) contains a cached copy of a portion of data in the compressed data region (L4).

6. The computer memory system according to claim 4, wherein data in the uncompressed data region (L3), in the absence of available space in the uncompressed data region (L3), are written to the compressed data region (L4) to make available space in the uncompressed data region (L3) after being compressed.

7. The computer memory system according to claim 4, wherein if an address of data requested by a general purpose processor is absent in the uncompressed data region (L3), then the data is retrieved from the uncompressed data region (L4) and the data retrieved from the compress data region (L4) is decompressed and written to the uncompressed data region (L3).

8. The computer memory system according to claim 1, wherein if an address of data requested by a general purpose processor is absent in the uncompressed data region (L3) and in compressed data region (N), then the data is retrieved from the second-type memory (L5) and the data retrieved from the second-type memory is decompressed and written to the uncompressed data region (L3).

9. The computer memory system according to claim 1, wherein the first-type memory contains a cached copy of a portion of the second-type memory (L5).

10. The computer memory system according to claim 1, wherein data in the first-type memory (L3 and L4), in the absence of available space, are written to the second-type memory (L5) to make available space in the first-type memory (L3 and L4).

11. The computer memory system according to claim 1, further comprising:

a multi-processor being connected to the computer memory system via one of;

Hyper Transport physical link, PCI express, InfiniBand, an industry standard, and a non-industry standard link;

a circuit carrier or a printed circuit board attaching the multi-processor, the first-type memory, the second-type memory, and the memory controller means and occupying at least one processor socket for the multi-processor, the multi-processor is one of;

Symmetric Multi-Processor and Heterogeneous Multi-Processor; and

a memory module encapsulating the first-type memory, the second-type memory, and the memory controller means and being plugged in the circuit carrier or the printed circuit board, the memory module is one of;

Dual In-line Memory Module (DIMM) and Single In-line Memory Module (SIMM).