Extending and Scavenging Super-Capacitor Capacity

• US 20090254772A1
• Filed: 04/08/2008
• Published: 10/08/2009
• Est. Priority Date: 04/08/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Elliott, John C., Kubo, Robert A., Lucas, Gregg S., Cagno, Brian J.
• Granted Patent: US 8,161,310 B2
• Time in Patent Office: Days
• US Class Current: 713/340
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/141 Battery and back-up supplies

Abstract

A memory system has mechanisms for scavenging capacity of a super capacitor by removing, or reducing, system load from the super capacitor when the super capacitor voltage decays below a low threshold. The mechanisms then restore the system load to the super capacitor when the super capacitor voltage ramps back above a high threshold. A controller may reduce system load by placing a volatile memory system in a standby state and disabling a field effect transistor to remove power from a non-volatile memory system. A controller may adjust the high threshold and/or a low threshold by setting a digitally controlled potentiometer in a threshold detect circuit via an I²C bus.

Claims

1. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:

transition to backup mode;

reduce system load on the hold-up voltage source responsive to a voltage level of the hold-up voltage source dropping below a low threshold; and

restore the system load on the hold-up voltage source and continuing operation of the backup mode responsive to the voltage level of the hold-up voltage source ramping up to a high threshold.

2. The computer program product of claim 1, wherein the computer readable program further causes the computing device to:

adjust the high threshold prior to restoring the system load on the hold-up voltage source.

3. The computer program product of claim 2, wherein the computer readable program further causes the computing device to:

determine whether the high threshold is within a predetermined range of the low threshold; and

stop operation of the backup mode responsive to the high threshold being within a predetermined range of the low threshold.

4. The computer program product of claim 2, wherein the backup mode comprises a memory backup mode to store data from a volatile memory to a non-volatile memory using power provided by a hold-up voltage source responsive to a power event, and wherein reducing system load on the hold-up voltage source comprises placing the volatile memory in a standby state.

5. The computer program product of claim 4, wherein restoring the system load on the hold-up voltage source comprises placing the volatile memory in a non-standby state.

6. The computer program product of claim 2, wherein the backup mode comprises a memory backup mode to store data from a volatile memory to a non-volatile memory using power provided by a hold-up voltage source responsive to a power event, and wherein reducing system load on the hold-up voltage source comprises disabling power to the non-volatile memory.

7. The computer program product of claim 6, wherein restoring the system load on the hold-up voltage source comprises enabling power to the non-volatile memory.

8. A method, in a data processing system, for scavenging hold-up voltage source capacity, the method comprising:

responsive to a power event, transitioning to a backup mode;

responsive to a voltage level of the hold-up voltage source dropping below a low threshold, reducing system load on the hold-up voltage source;

responsive to the voltage level of the hold-up voltage source ramping up to a high threshold, restoring the system load on the hold-up voltage source and continuing operation of the backup mode.

9. The method of claim 8, further comprising:

prior to restoring the system load on the hold-up voltage source, adjusting the high threshold.

10. The method of claim 9, further comprising:

determining whether the high threshold is within a predetermined range of the low threshold; and

responsive to the high threshold being within a predetermined range of the low threshold, stopping operation of the backup mode.

11. The method of claim 8, wherein the backup mode comprises a memory backup mode to store data from a volatile memory to a non-volatile memory using power provided by a hold-up voltage source responsive to a power event, and wherein reducing system load on the hold-up voltage source comprises placing the volatile memory in a standby state.

12. The method of claim 11, wherein restoring the system load on the hold-up voltage source comprises placing the volatile memory in a non-standby state.

13. The method of claim 8, wherein the backup mode comprises a memory backup mode to store data from a volatile memory to a non-volatile memory using power provided by a hold-up voltage source responsive to a power event, and wherein reducing system load on the hold-up voltage source comprises disabling power to the non-volatile memory.

14. The method of claim 13, wherein restoring the system load on the hold-up voltage source comprises enabling power to the non-volatile memory.

15. The method of claim 8, wherein the hold-up voltage source is a super capacitor.

16. A memory system comprising:

a controller, wherein the controller is configured to detect a power event from a power supply that provides power to a storage controller and the memory system;

a volatile memory;

a non-volatile memory; and

a hold-up voltage source, wherein the hold-up voltage source is configured to provide power to the memory system responsive to the power event,

wherein the controller is configured to transition to memory backup mode to store data from the volatile memory to the non-volatile memory using power provided by the hold-up voltage source responsive to the power event, reduce system load on the hold-up voltage source responsive to a voltage level of the hold-up voltage source dropping below a low threshold, and restore the system load on the hold-up voltage source and continuing operation of the backup mode responsive to the voltage level of the hold-up voltage source ramping up to a high threshold.

17. The memory system of claim 16, further comprising:

a low threshold detect circuit that generates a low threshold detect signal responsive to the voltage level of the hold-up voltage source dropping below a low threshold; and

a high threshold detect circuit that generates a high threshold detect signal responsive to the voltage level of the hold-up voltage source ramping up to the high threshold.

18. The memory system of claim 17, wherein the low threshold detect circuit comprises:

a comparator that compares a first reference voltage to a second reference voltage, wherein the first reference voltage is derived from the voltage level of the hold-up voltage source and wherein the second reference voltage is derived from a Zener voltage of a Zener diode.

19. The memory system of claim 17, wherein the high threshold detect circuit comprises:

a comparator that compares a first reference voltage to a second reference voltage, wherein the first reference voltage is derived from the voltage level of the hold-up voltage source and wherein the second reference voltage is derived from a Zener voltage of a Zener diode using a voltage divider.

20. The memory system of claim 19, wherein the voltage divider comprises a digitally controlled potentiometer and wherein the controller sets the high threshold by setting the digitally controlled potentiometer.