DIGITAL RELIABILITY MONITOR HAVING AUTONOMIC REPAIR AND NOTIFICATION CAPABILITY

• US 20090254781A1
• Filed: 06/08/2009
• Published: 10/08/2009
• Est. Priority Date: 12/04/2003
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bonaccio, Anthony R., Ventrone, Sebastian T., Tonti, William R., LeStrange, Michael
• Granted Patent: US 7,966,537 B2
• Time in Patent Office: Days
• US Class Current: 714/48
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom

Abstract

A circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter configured to count pulses of a pulsed signal, the repair processor configured to (a) replace the original circuit with a first redundant circuit or (b) configured to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of pre-determined cycle counts.

Claims

1. An integrated circuit, comprising:

an original circuit;

two or more redundant circuits;

a clock cycle counter configured to count cycles of a clock signal; and

a repair processor, said repair processor responsive to said clock cycle counter to;

(a) replace said original circuit with a first redundant circuit when said cycle counter reaches an initial predetermined count of a set of counts;

after (a), (b) replace a previously selected redundant circuit with another redundant circuit each time that said clock cycle counter reaches subsequent predetermined counts of said set of counts; and

(c) repeat (b) until no unselected redundant circuits have been selected.

2. The integrated circuit of claim 1, further including:

a robust redundant circuit; and

said repair processor further configured to replace said last redundant circuit with said robust redundant circuit when said clock cycle counter reaches a last count of said set of predetermined counts.

3. The integrated circuit of claim 1, wherein said repair processor is responsive to said clock cycle counter to:

(d), replace a last selected redundant circuit with a different circuit each time said cycle counter reaches subsequent predetermined counts of said set of counts, said different circuit selected from the group consisting of said original circuit and one of said two or more redundant circuits, in the sequence from said original circuit to said first redundant circuit through said last redundant circuit and back to said original circuit.

4. The integrated circuit of claim 3, further including:

an error detection circuit configured to determine if said original circuit and if any of said one or more redundant circuits has failed;

a tracking register coupled between said error detection and said repair processor, said tracking register for storing information marking failed original circuits and failed redundant circuits as failed circuits; and

said repair processor is further configured to not replace said original circuit and any redundant circuit with a failed circuit.

5. The integrated circuit of claim 1, further including:

a stress reduction circuit coupled to said original circuit and said one or more redundant circuits and responsive to said repair processor; and

said stress reduction circuit configured to modify one or more operating parameters of said original circuit, of said one or more redundant circuits or of said original circuit and said one or more redundant circuits when said clock cycle counter reaches a particular pre-determined count of said set of counts.

6. The integrated circuit of claim 1, wherein said stress reduction circuit is selected from the group consisting of voltage regulator circuits, switching circuits configured to select a frequency of said pulsed signal, pulse generating circuits configured to select said frequency of said pulsed signal, bias circuits configured to select a bias voltage to apply to bodies of transistors in said original circuit, said one or more redundant circuits or both said original circuit and said one or more redundant circuits, and combinations thereof.

7. The integrated circuit of claim 1, wherein said original circuit and said one or more redundant circuits are selected from the group consisting of a digital circuit, an analog circuit, a memory circuit, a latch, a logic gate, a group of logic gates, a transistor, a diode, a resistors, capacitor, an inductor and a wire.

8. The integrated circuit of claim 1, further including:

wherein said clock cycle counter comprises one or more sub-clock cycle counters each having a latch configured to store a running total count of cycles of said clock signal; and

a decode circuit coupled to said latches of said sub-clock cycle counters, said decode circuit configured to replace a particular sub-clock cycle counter with a different sub-clock cycle counter each time said running total count reaches predetermined counts of said set of counts.

9. An integrated circuit, comprising:

an original circuit;

a clock cycle counter configured to count cycles of a clock signal; and

a stress reduction circuit coupled to said original circuit and coupled to and responsive to a repair processor, said stress reduction circuit configured to modify one or more operating parameters of said original circuit when said clock cycle counter reaches a particular pre-determined count of cycles of said clock signal.

10. The integrated circuit of claim 9, wherein said stress reduction circuit is selected from the group consisting of voltage regulator circuits, switching circuits configured to select a frequency of said pulsed signal, pulse generating circuits configured to select said frequency of said pulsed signal, bias circuits configured to select a bias voltage to apply to bodies of transistors in said original circuit, said one or more redundant circuits or both said original circuit and said one or more redundant circuits, and combinations thereof.