METHODS AND SYSTEMS FOR PLACEMENT AND ROUTING
3 Assignments
0 Petitions
Accused Products
Abstract
Techniques for placement of integrated circuit elements include global placement, detailed placement, timing closure, and routing. The integrated circuit is described by a netlist specifying interconnections of morphable devices. The detailed placement uses, for example, Simultaneous Dynamical Integration, wherein the morphable-devices correspond to nodes influenced by forces, including timing forces. The timing forces are derived, for example, from a timing graph; path delay; slack; and drive resistance of the elements. The timing closure uses timing-driven buffering and timing-driven resizing to reduce maximum delay and/or transition time, and/or to fix hold time. Nets having high capacitance and/or fanout, and timing critical nets are preferentially processed. Timing-driven buffering applies buffering solutions to segments of route trees, combines solutions of adjoining segments, and prunes sets of solutions. Timing-driven resizing morphably replaces selected elements with upsized versions thereof.
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Citations
30 Claims
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1-10. -10. (canceled)
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11. A method comprising:
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replacing, by a computing apparatus, a first driver of a first net of a plurality of nets of a design of an integrated circuit with a second driver, wherein the first driver and the second driver have different drive strengths; and inserting, by a computing apparatus, a buffer driving a second net of the plurality of the nets based at least in part on a timing of the design. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A computer readable medium having stored thereon, computer-executable instructions that, if executed by a computing apparatus, cause the computing apparatus to perform a method comprising:
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replacing a first driver of a first net of a plurality of nets of a design of an integrated circuit with a second driver, wherein the first driver and the second driver have different drive strengths; and inserting a buffer driving a second net of the plurality of the nets based at least in part on a timing of the design. - View Dependent Claims (23, 24, 25)
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26. A system comprising:
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a processor; and a computer-readable medium coupled to the processor by way of a bus, the computer-readable medium having stored thereon, computer-executable instructions that, if executed by the processor, cause the system to perform a method comprising; replacing a first driver of a first net of a plurality of nets of a design of an integrated circuit with a second driver, wherein the first driver and the second driver have different drive strengths; and inserting a buffer driving a second net of the plurality of the nets based at least in part on a timing of the design. - View Dependent Claims (27, 28, 29, 30)
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Specification