Method of Creating Alignment/Centering Guides for Small Diameter, High Density Through-Wafer Via Die Stacking

• US 20090255705A1
• Filed: 04/11/2008
• Published: 10/15/2009
• Est. Priority Date: 04/11/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pratt, Dave
• Granted Patent: US 9,136,259 B2
• Time in Patent Office: Days
• US Class Current: 174/98
• CPC Class Codes: H01L 2224/10135 Alignment aids
• CPC Class Codes: H01L 2224/10165 Alignment aids
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/8014 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/81139 Guiding structures on the body
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing

Abstract

A method if provided for forming a die stack. The method includes forming a plurality of through-wafer vias and a first plurality of alignment features in a first die. A second plurality of alignment features is formed in a second die, and the first die is stacked on the second die such that the first plurality of alignment features engage the second plurality of alignment features. A method of manufacturing a die stack is also provided that includes forming a plurality of through-wafer vias on a first die, forming a plurality of recesses on a first die, and forming a plurality of protrusions on a second die. A die stack and a system are also provided.

Claims

1. A method of forming a die stack, comprising:

forming a plurality of through-wafer vias in a first die; and

forming one or more alignment features in a first die.

2. The method of claim 1, comprising creating one or more alignment features in a second die.

3. The method of claim 1, comprising stacking the second die on the first die.

4. The method of claim 1, wherein the alignment features comprise a plurality of openings.

5. The method of claim 1, wherein the plurality of openings extend at least as far from the surface of the die as the plurality of through-wafer vias.

6. The method of claim 1, wherein the alignment features comprise a plurality of protrusions extending from the die.

7. The method of claim 1, wherein forming the one or more alignment features comprises forming the alignment features by photolithography, stereolithography, wet etch, dry etch, passivation, or a combination thereof.

8. The method of claim 1, comprising picking the first die and placing the first die onto the second die such that the alignment features of the first die engage the alignment features of the second die.

9. The method of claim 1, comprising placing the die stack in a curing oven.

11. The method of claim 9, comprising stacking the first die onto the second die such that the plurality of recesses engage the plurality of protrusions.

12. The method of claim 9, comprising stacking the second die onto the first die such that the plurality of protrusions engage the plurality of recesses.

13. The method of claim 9, wherein forming the plurality of recesses on a first die comprises forming a plurality of recesses in a layer disposed on the first day.

14. The method of claim 12, wherein the layer comprises a passivation layer.

18. The die stack of claim 9, wherein the plurality of bond pads of the second die are configured to engage the plurality of through-wafer vias of the first die.

10. A method of manufacturing a die stack, comprising:

forming a plurality of through-wafer vias on a first die;

forming a plurality of recesses on a first die; and

forming a plurality of protrusions on a second die, wherein the plurality of protrusions are configured to engage the plurality of recesses to align a plurality of bond pads of the second die with the plurality of through-wafer vias of the first die.

15. A method of manufacturing a semiconductor device, comprising:

forming a plurality of alignment features in a wafer;

dicing the wafer into a plurality of dies, such that each die comprises one or more of the plurality of alignment features;

forming a plurality of through-wafer vias in a first die of the plurality of dies.

16. The method of claim 15, wherein forming a plurality of alignment features comprising forming the plurality of alignment features at a plurality of die streets of the wafer.

19. The die stack of claim 15, wherein the first plurality of alignment features comprises a plurality of recesses.

21. The die stack of claim 15, wherein the first plurality of alignment features and the second plurality of alignment features comprise a plurality of protrusions.

23. The system of claim 21, wherein the die stack of claim 21, wherein the die stack comprises a second die having a second plurality of alignment features.

17. A die stack, comprising:

a first die having a first plurality of alignment features and a plurality of through-wafer vias; and

a second die having a second plurality of alignment features and a plurality of bond pads, wherein the second plurality of alignment features of the second die are configured to engage the first plurality of alignment features of the first die, such that the plurality of bond pads of the second die align with the plurality of through-wafer vias of the first die.

20. The die stack of claim 17 wherein the second plurality of alignment features comprises a plurality of protrusions extending from the surface of the die.

22. A system comprising:

an electronic device comprising;

a processor;

one or more semiconductor devices, wherein the one more semiconductor devices comprises a die stack, wherein the die stack comprises a first die having a first plurality of alignment features and through-wafer vias.

24. A die stack, comprising:

a first die having a first plurality of protrusions and a plurality of through-wafer vias; and

a second die having a second plurality of protrusions, wherein the second plurality of protrusions are configured to engage the first plurality of protrusions.