SPLIT GATE NON-VOLATILE MEMORY CELL WITH IMPROVED ENDURANCE AND METHOD THEREFOR
First Claim
1. A non-volatile memory cell comprising:
- a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region;
a select gate structure formed over the substrate, wherein the select gate structure overlies a first portion of the channel region;
a control gate structure formed adjacent to the select gate structure, wherein the control gate structure overlies a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of a radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.
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Abstract
A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.
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Citations
20 Claims
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1. A non-volatile memory cell comprising:
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a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region; a select gate structure formed over the substrate, wherein the select gate structure overlies a first portion of the channel region; a control gate structure formed adjacent to the select gate structure, wherein the control gate structure overlies a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of a radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5. - View Dependent Claims (2, 3, 4, 5)
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6. A non-volatile memory cell comprising:
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a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region; a select gate structure formed over the substrate, wherein the select gate structure overlies a first portion of the channel region; a control gate structure formed adjacent to the select gate structure, wherein the control gate structure overlies a second portion of the channel region, wherein the first portion and the second portion overlap, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of a radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5. - View Dependent Claims (7, 8, 9)
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10. A method of forming a non-volatile memory cell comprising:
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forming a polysilicon layer overlying a first insulating layer formed over a substrate; etching the polysilicon layer to form a select gate structure formed overlying the first insulating layer, wherein the select gate structure has at least one concave sidewall; forming a second insulating layer over the select gate structure and overlying at least a portion of the substrate; forming a layer of nanocrystals overlying at least a portion of the second insulating layer; forming a third insulating layer overlying the layer of nanocrystals; and forming a control gate structure adjacent to the select gate structure, wherein the control gate structure has a convex sidewall facing the at least one concave sidewall of the select gate structure. - View Dependent Claims (11, 12, 13, 17)
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14. A method of forming a non-volatile memory cell comprising:
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forming a polysilicon layer overlying a first insulating layer formed over a substrate; etching the polysilicon layer to form an inverted-T select gate structure formed overlying the first insulating layer, wherein the inverted-T select gate structure has a concave shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the inverted-T select gate structure; forming a second insulating layer overlying the inverted-T select gate structure; forming a layer of nanocrystals overlying at least a portion of the second insulating layer; forming a third insulating layer overlying the layer of nanocrystals; and forming a control gate structure adjacent to the inverted-T select gate structure, wherein the control gate structure has a convex shape facing the corner region. - View Dependent Claims (15, 16)
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18. A method of forming a non-volatile memory cell comprising:
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forming a polysilicon layer overlying a first insulating layer formed over a substrate; etching the polysilicon layer to form a U-shaped polysilicon region, wherein the U-shaped polysilicon region has a concave shape in a first corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a first inside surface of the U-shaped polysilicon region, and wherein the U-shaped polysilicon has a concave shape in a second corner region formed at an intersection of a third plane substantially parallel to the top surface of the substrate and a fourth plane substantially parallel to a second inside surface of the U-shaped polysilicon region; etching a portion of the U-shaped polysilicon region to form a control gate region; forming a second insulating layer overlying the control gate region and a remaining portion of the U-shaped polysilicon region; forming a layer of nanocrystals overlying at least a portion of the second insulating layer; forming a third insulating layer overlying the layer of nanocrystals; and forming a first select gate structure, a second select gate structure, a first control gate structure adjacent to the first select gate structure, and a second control gate structure adjacent to the second select gate structure, wherein the first control gate structure has a convex shape facing the first corner region, and the second control gate structure has a convex shape facing the second corner region. - View Dependent Claims (19, 20)
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Specification