SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20090256197A1
• Filed: 03/09/2009
• Published: 10/15/2009
• Est. Priority Date: 04/09/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Matsuura, Hitoshi, NAKAZAWA, Yoshito
• Granted Patent: US 7,999,345 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench.

Claims

1. A semiconductor device including a first region having a Schottky barrier diode formed therein and a second region having a power MISFET formed therein,

the first region comprising:

(a1) a semiconductor substrate of a first conductivity type having an upper surface and a lower surface on a side opposite to the upper surface;

(a2) a first semiconductor layer of the first conductivity type formed over the upper surface of the semiconductor substrate;

(a3) a second semiconductor layer of the first conductivity type formed over the first semiconductor layer;

(a4) a first metal film formed over the second semiconductor layer, the first metal film and the second semiconductor layer forming a Schottky junction; and

(a5) a second metal film formed over the lower surface of the semiconductor substrate,

the second region comprising;

(b1) the semiconductor substrate;

(b2) the first semiconductor layer formed over the semiconductor substrate;

(b3) a channel region formed in the first semiconductor layer and having a second conductivity type opposite to the first conductivity type;

(b4) a trench penetrating through the channel region and reaching the first semiconductor layer;

(b5) a gate insulating film formed over an inner wall of the trench;

(b6) a gate electrode formed over the gate insulating film and filled in the trench;

(b7) a source region of the first conductivity type contiguous to the trench and formed over the channel region;

(b8) the first metal film formed over the source region and electrically coupled to the source region; and

(b9) the second metal film formed over the lower surface of the semiconductor substrate,

wherein the first metal film functions as an anode electrode of the Schottky barrier diode in the first region and as a source electrode of the power MISFET in the second region,

wherein the second metal film functions as a cathode electrode of the Schottky barrier diode in the first region and as a drain electrode of the power MISFET in the second region,

wherein the second semiconductor layer has a doping concentration lower than that of the first semiconductor layer, and

wherein a boundary between the first semiconductor layer and the second semiconductor layer is formed in a region as deep as the bottom portion of the trench or in a region shallower than the bottom portion of the trench.

2. The semiconductor device according to claim 1, wherein the doping concentration of the second semiconductor layer becomes higher with the depth from the surface of the second semiconductor layer in which the Schottky junction has been formed.

3. The semiconductor device according to claim 2, wherein the doping concentration in the surface of the second semiconductor layer in which the Schottky junction has been formed is 8.0×

10¹⁵/cm³ or less.

4. The semiconductor device according to claim 1, wherein the doping concentration of the second semiconductor layer is constant from the surface of the second semiconductor layer where the Schottky junction has been formed to a predetermined depth, and the doping concentration increases as the depth becomes greater than the predetermined depth.

5. The semiconductor device according to claim 4, wherein the doping concentration of the second semiconductor layer from the surface to the predetermined depth is 8.0×

10¹⁵/cm³ or less.

6. The semiconductor device according to claim 1, wherein the doping concentration of the first semiconductor layer increases from the boundary between the first semiconductor layer and the second semiconductor layer toward the boundary between the first semiconductor layer and the semiconductor substrate.

7. The semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are epitaxial layers.

8. The semiconductor device according to claim 1, wherein the first metal film comprises a barrier conductor film and a metal film formed over the barrier conductor film.

9. The semiconductor device according to claim 8, wherein the Schottky junction of the Schottky barrier diode is formed by a contact between the second semiconductor layer and the barrier conductor film.

10. The semiconductor device according to claim 9, wherein the barrier conductor film is a titanium tungsten film.

11. The semiconductor device according to claim 9, wherein the barrier conductor film is a titanium nitride/titanium film stack.

12. The semiconductor device according to claim 9, wherein the barrier conductor film is a cobalt film.

13. The semiconductor device according to claim 8, wherein the metal film is an aluminum film.

14. The semiconductor device according to claim 1, wherein the Schottky barrier diode and the power MISFET are parts of a plurality of elements configuring a DC/DC converter for converting a voltage value of a DC current voltage.

15. The semiconductor device according to claim 14,

wherein the power MISFET is a synchronous rectification power MISFET configuring the DC/DC converter, and

wherein the Schottky barrier diode is coupled in parallel to the power MISFET.

16. The semiconductor device according to claim 1, wherein the second region further comprises:

(b10) a contact hole arranged apart from the trench and having a depth greater than that of the source region;

(b11) a body contact region formed below the bottom portion of the contact hole and comprising a semiconductor region of the second conductivity type; and

(b12) a first semiconductor region contiguous to the body contact region and comprising a semiconductor region of the second conductivity type formed in a region deeper than the body contact region, and

wherein the contact hole is filled with the first metal film.

17. The semiconductor device according to claim 16, wherein the doping concentration of the body contact region is higher than the doping concentration of the first semiconductor region.

18. The semiconductor device according to claim 17,

wherein the first region is sandwiched between the second regions, and

wherein the first region has, at both ends thereof, well layers comprising a semiconductor layer of the second conductivity type so as to sandwich the Schottky barrier diode formed in the first region between the well layers, and

wherein the doping concentration of the well layers is different from the doping concentration of the channel region formed in the second region.

19. The semiconductor device according to claim 18, wherein the first region further comprises:

(a6) a second semiconductor region of the second conductivity type which is contiguous to the first metal film and arranged in the well layer; and

(a7) a third semiconductor layer of the second conductivity type which is contiguous to the second semiconductor region and formed in a region deeper than the second semiconductor region,

wherein the second semiconductor region formed in the first region has a similar structure to that of the body contact region formed in the second region, and

wherein the third semiconductor region formed in the first region has a similar structure to that of the first semiconductor region formed in the second region.

20. A manufacturing method of a semiconductor device, comprising the steps of:

(a) preparing a multilayer substrate having a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type formed over the semiconductor substrate, and a second semiconductor layer of the first conductivity type formed over the first semiconductor layer and having a doping concentration lower than that of the first semiconductor layer;

(b) forming a trench in a second region of the multilayer substrate in which a power MISFET is to be formed;

(c) forming a gate insulating film over an inner wall of the trench;

(d) forming a gate electrode over the gate insulating film so as to fill the trench with the gate electrode;

(e) forming a channel region of a second conductivity type opposite to the first conductivity type in the second region of the multilayer substrate;

(f) forming, in the second region of the multilayer substrate, a source region contiguous to the trench and comprising a semiconductor region of the first conductivity type;

(g) forming a first metal film which is contiguous to the source region in the second region of the multilayer substrate and which is contiguous to the second semiconductor layer to form a Schottky junction in a first region of the multilayer substrate in which a Schottky barrier diode is to be formed; and

(h) forming a second metal film over a lower surface of the semiconductor substrate included in the multilayer substrate,

wherein the first metal film serves as a source electrode of the power MISFET in the second region and serves as an anode electrode of the Schottky barrier diode in the first region,

wherein the second metal film serves as a drain electrode of the power MISFET in the second region and serves as a cathode electrode of the Schottky barrier diode in the first region, and

wherein, after completion of the power MISFET and the Schottky barrier diode, a boundary between the first semiconductor layer and the second semiconductor layer is present in a region as deep as or shallower than the bottom portion of the trench.

21. The manufacturing method of a semiconductor device according to claim 20, wherein the second semiconductor layer after completion of the power MISFET and the Schottky barrier diode includes a residual region having a doping concentration equal to that of the second semiconductor layer during the step (a).

22. The manufacturing method of a semiconductor device according to claim 21, wherein the steps until the completion of the power MISFET and the Schottky barrier diode comprise a step of heat treating the multilayer substrate.

23. The manufacturing method of a semiconductor device according to claim 22, wherein the heat treatment step decreases the thickness of the second semiconductor layer.

24. The manufacturing method of a semiconductor device according to claim 22, wherein the boundary between the second semiconductor layer and the first semiconductor layer becomes shallower by the heat treatment step.

25. The manufacturing method of a semiconductor device according to claim 24, wherein the doping concentration of the first semiconductor layer increases from a shallow region in which the upper surface of the first semiconductor layer has been formed toward a deep region in which the lower surface of the first semiconductor layer has been formed.