Low switching current MTJ element for ultra-high STT-RAM and a method for making the same
First Claim
1. A MTJ nanopillar structure in a STT-RAM device, comprising:
- (a) a first stack of layers with sidewalls formed on a bottom electrode and having a thickness in a direction perpendicular to said bottom electrode and a first shape with a first area in a plane orthogonal to said thickness direction, comprising;
(1) a seed layer on the bottom electrode;
(2) a composite reference magnetic layer formed on the seed layer and comprised of at least one magnetic layer and an insertion layer that induces a high damping constant in said at least one magnetic layer, and wherein the at least one magnetic layer with a high damping constant is a reference layer in a “
self-pinned”
state with a first thickness and a magnetization direction along an easy axis direction in a plane orthogonal to said thickness direction; and
(3) a tunnel barrier layer on the “
self-pinned”
reference magnetic layer(b) a second stack of layers with sidewalls formed on the first stack of layers and having a thickness in a direction perpendicular to said bottom electrode and a second shape with a second area substantially less than the first area in a plane orthogonal to said thickness direction;
comprising(1) a composite free layer having a FM1/NCC/FM2 configuration wherein NCC is a nanocurrent channel layer comprised of R(Si) grains formed in an oxide or nitride insulator matrix and R is Fe, Ni, Co, or B, and the FM1 and FM2 layers are magnetic layers having a low damping constant and a combined thickness substantially less than the first thickness of the reference layer;
(2) a Ru capping layer on the composite free layer; and
(3) a hard mask formed on the capping layer.
3 Assignments
0 Petitions
Accused Products
Abstract
A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R is disclosed. The MTJ has a MgO tunnel barrier formed by natural oxidation to achieve a low RA, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel layer to minimize Jc0. There is a thin Ru capping layer for a spin scattering effect. The reference layer has a shape anisotropy and Hc substantially greater than that of the free layer to establish a “self-pinned” state. The free layer, capping layer and hard mask are formed in an upper section of a nanopillar that has an area substantially less than a lower pedestal section which includes a bottom electrode, reference layer, seed layer, and tunnel barrier layer. The reference layer is comprised of an enhanced damping constant material that may be an insertion layer, and the free layer has a low damping constant.
148 Citations
27 Claims
-
1. A MTJ nanopillar structure in a STT-RAM device, comprising:
-
(a) a first stack of layers with sidewalls formed on a bottom electrode and having a thickness in a direction perpendicular to said bottom electrode and a first shape with a first area in a plane orthogonal to said thickness direction, comprising; (1) a seed layer on the bottom electrode; (2) a composite reference magnetic layer formed on the seed layer and comprised of at least one magnetic layer and an insertion layer that induces a high damping constant in said at least one magnetic layer, and wherein the at least one magnetic layer with a high damping constant is a reference layer in a “
self-pinned”
state with a first thickness and a magnetization direction along an easy axis direction in a plane orthogonal to said thickness direction; and(3) a tunnel barrier layer on the “
self-pinned”
reference magnetic layer(b) a second stack of layers with sidewalls formed on the first stack of layers and having a thickness in a direction perpendicular to said bottom electrode and a second shape with a second area substantially less than the first area in a plane orthogonal to said thickness direction;
comprising(1) a composite free layer having a FM1/NCC/FM2 configuration wherein NCC is a nanocurrent channel layer comprised of R(Si) grains formed in an oxide or nitride insulator matrix and R is Fe, Ni, Co, or B, and the FM1 and FM2 layers are magnetic layers having a low damping constant and a combined thickness substantially less than the first thickness of the reference layer; (2) a Ru capping layer on the composite free layer; and (3) a hard mask formed on the capping layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A MTJ nanopillar structure in a STT-RAM device, comprising:
-
(a) a first stack of layers formed on a bottom electrode and having a thickness in a direction perpendicular to said bottom electrode and a first shape with a first area in a plane orthogonal to said thickness direction, comprising; (1) a seed layer formed on said bottom electrode; (2) a composite SyAF reference magnetic layer formed on the seed layer and comprised of a AP1 and AP2 magnetic layers, an anti-ferromagnetic coupling layer, and an insertion layer that induces a high damping constant in at least one of the AP1 and AP2 magnetic layers, and wherein the AP1 magnetic layer contacts an overlying tunnel barrier layer and is in a “
self-pinned”
state with a first thickness and a magnetization direction along an easy axis direction in a plane orthogonal to said thickness direction; and(3) a tunnel barrier layer on the “
self-pinned”
reference magnetic layer(b) a second stack of layers with sidewalls formed on the first stack of layers and having a thickness in a direction perpendicular to said bottom electrode and a second shape with a second area in a plane orthogonal to said thickness direction, said first area is from 0% to about 900% greater than the second area;
comprising(1) a composite free layer having a FM1/NCC/FM2 configuration wherein NCC is a nanocurrent channel layer comprised of R(Si) grains formed in an oxide or nitride insulator matrix and R is Fe, Ni, Co, or B, and the FM1 and FM2 layers are magnetic layers having a low damping constant and a combined thickness substantially less than the first thickness of the reference layer; (2) a Ru capping layer on the composite free layer; and (3) a hard mask formed on the capping layer. - View Dependent Claims (11, 12, 13, 14, 15, 16)
-
-
17. A method of forming a STT-RAM MTJ nanopillar on a substrate wherein said substrate has a via stud formed in a first dielectric layer and an overlying bottom electrode layer that contacts said via stud and has a planar top surface, comprising:
-
(a) sequentially forming a MTJ stack of layers comprised of a seed layer, composite reference layer having an upper “
self-pinned”
magnetic layer with a thickness and an insertion layer that induces a high damping constant in the “
self-pinned”
magnetic layer, a tunnel barrier layer, a composite free layer having a FM1/RSiO/FM2 configuration, a capping layer, and a hard mask on the bottom electrode layer wherein said RSiO layer is comprised of R(Si) grains in a silicon oxide matrix and FM1 and FM2 are magnetic layers;(b) patterning the composite free layer, capping layer, and hard mask to form an upper section of said nanopillar having sidewalls, a certain thickness in a direction perpendicular to said planar top surface and a first shape with a first area in a plane parallel to said planar top surface, said patterning process exposes a portion of the tunnel barrier layer; (c) depositing a passivation layer on said upper section of the nanopillar, along said sidewalls, and on the exposed portion of the tunnel barrier layer; and (d) patterning the tunnel barrier layer, composite reference layer, and seed layer to form a lower pedestal section having sidewalls and a second shape with a second area in a plane parallel to said planar top surface, said lower pedestal section and the upper section are formed above said via stud, and said passivation layer remains only along the sidewalls in the second stack of layers. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
-
Specification