MEMS power inductor and method of forming the MEMS power inductor

• US 20090256667A1
• Filed: 04/09/2008
• Published: 10/15/2009
• Est. Priority Date: 04/09/2008
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Smeys, Peter, Johnson, Peter
• Granted Patent: US 8,044,755 B2
• Time in Patent Office: Days
• US Class Current: 336/175
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0066 with a magnetic layer
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate inductors for integrated circuits H01L28/10
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49073 by assembling coil and core
• CPC Class Codes: Y10T 29/49075 including permanent magnet or core
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace.

Claims

1. A semiconductor inductor comprising:

a lower mold to touch a semiconductor die, the lower mold being non-conductive and having a pair of openings that expose a pair of conductive members of the semiconductor die;

a plurality of spaced-apart magnetic lower laminations to touch the lower mold;

a magnetic gap layer to touch the lower mold and the magnetic lower laminations, the magnetic gap layer being non-conductive;

a pair of conductive plugs to touch the magnetic gap layer, and touch and extend through the lower mold to make electrical connections with the pair of conductive members; and

a conductive trace to touch the magnetic gap layer and the pair of conductive plugs, and lie directly over each of the magnetic lower laminations.

2. The semiconductor inductor of claim 1 and further comprising an upper mold to touch the magnetic gap layer and the conductive trace, the upper mold being non-conductive.

3. The semiconductor inductor of claim 2 wherein the upper mold has a pair of openings that expose the pair of conductive plugs.

4. The semiconductor inductor of claim 2 and further comprising a plurality of spaced-apart magnetic upper laminations to touch the upper mold, each magnetic upper lamination directly lying over the conductive trace.

5. The semiconductor inductor of claim 4 wherein each magnetic lower lamination is electrically isolated from each other.

6. The semiconductor inductor of claim 5 wherein each magnetic upper lamination is electrically isolated from each other.

7. The semiconductor inductor of claim 6 wherein the conductive trace is electrically isolated from the magnetic lower laminations and the magnetic upper laminations.

8. The semiconductor inductor of claim 6 wherein the pair of conductive plugs is electrically isolated from the magnetic lower laminations and the magnetic upper laminations.

9. The semiconductor inductor of claim 4 wherein each magnetic upper lamination includes a horizontal member and a pair of spaced-apart vertical members that extend away from the horizontal member.

10. The semiconductor inductor of claim 4 wherein the conductive trace is circular.

11. The semiconductor inductor of claim 4 wherein the magnetic lower laminations and the magnetic upper laminations form a magnetic core structure.

12. A method of forming a semiconductor inductor comprising:

forming a lower mold to touch a semiconductor die, the lower mold being non-conductive and having a pair of openings that expose a pair of conductive members of the semiconductor die;

forming a plurality of spaced-apart magnetic lower laminations to touch the lower mold;

forming a magnetic gap layer to touch the lower mold and the magnetic lower laminations, the magnetic gap layer being non-conductive; and

forming a conductive structure to touch the magnetic gap layer, and touch and extend through the lower mold to make electrical connections with the pair of conductive members, the conductive structure including a pair of plug structures and a trace structure that touches the pair of plug structures.

13. The method of claim 12 wherein the trace structure lies directly over each of the magnetic lower laminations.

14. The method of claim 13 and further comprising forming an upper mold to touch the magnetic gap layer and the conductive trace, the upper mold being non-conductive.

15. The method of claim 14 wherein the upper mold has a pair of openings that expose the pair of conductive plugs.

16. The method of claim 14 and further comprising forming a plurality of spaced-apart magnetic upper laminations to touch the upper mold, each magnetic upper lamination lying directly over the conductive trace.

17. The method of claim 16 wherein the conductive structure is electrically isolated from the magnetic lower laminations and the magnetic upper laminations.