METHOD AND SYSTEM FOR MAC AND PHY SYNCHRONIZATION FOR ENERGY EFFICIENT NETWORKING

• US 20090257457A1
• Filed: 03/31/2009
• Published: 10/15/2009
• Est. Priority Date: 04/15/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Diab, Wael William
• Granted Patent: US 8,565,269 B2
• Time in Patent Office: Days
• US Class Current: 370/503
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: H04J 3/0635 Clock or time synchronisation in a network timer in protocols H04L69/28
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 2007/045 Fill bit or bits, idle words
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Aspects of a method and system for MAC and PHY synchronization for energy efficient networking are provided. In this regard, an interface that enables communication between a MAC controller and a PHY device may be configured to operate in an energy saving mode. While the interface is operating in an energy saving mode, synchronization between the MAC controller and the PHY device may be maintained by one or both of adjusting a clock generated for the interface and/or communicating dummy data via the interface. The clock may be adjusted by one or more of adjusting a frequency of the clock, adjusting an amplitude of the clock, and/or duty cycling the clock. The MAC controller and/or the PHY device may generate the dummy data. The PHY device and/or the MAC controller may discard the dummy data upon receiving the dummy data.

Claims

1. A method for networking, the method comprising:

configuring an interface that enables communication between a MAC controller and a PHY device to operate in an energy saving mode; and

while said interface is operating in said energy saving mode, maintaining synchronization between said MAC controller and said PHY device by one or both of adjusting a clock generated for said interface and/or communicating dummy data via said interface.

2. The method according to claim 1, comprising adjusting said clock by one or more of:

adjusting a frequency of said clock generated for said interface;

adjusting an amplitude of said clock; and

/or

duty cycling said clock.

3. The method according to claim 1, comprising adjusting said clock periodically and/or aperiodically over one or more time intervals.

4. The method according to claim 1, comprising configuring said interface to operate in said energy saving mode at a time instant determined by one or both of a rate at which data is to be communicated by said interface and/or an amount of data to be communicated by said interface.

5. The method according to claim 4, comprising determining said amount of data to be communicated by said interface based on a status of one or more queues in said PHY device and/or said MAC controller.

6. The method according to claim 1, wherein said interface exits from said energy saving mode when said interface receives data from said MAC controller and/or when said interface receives data from said PHY device.

7. The method according to claim 1, wherein said MAC controller generates said dummy data.

8. The method according to claim 7, wherein said PHY device discards said dummy data when said dummy data is received by said PHY device.

9. The method according to claim 1, wherein said PHY device generates said dummy data.

10. The method according to claim 9, wherein said MAC controller discards said dummy data when said dummy data is received by said MAC device.

12. The system according to claim 1, wherein said clock is adjusted by one or more of:

adjusting a frequency of said clock generated for said interface;

adjusting an amplitude of said clock; and

/or

duty cycling said clock.

13. The system according to claim 1, wherein said clock is adjusted periodically and/or aperiodically over one or more time intervals.

14. The system according to claim 1, wherein said interface is configured to operate in said energy saving mode at a time instant determined by one or both of a rate at which data is to be communicated by said interface and/or an amount of data to be communicated by said interface.

15. The system according to claim 4, wherein said amount of data to be communicated by said interface is determined based on a status of one or more queues in said PHY device and/or said MAC controller.

16. The system according to claim 1, wherein said interface exits from said energy saving mode when said interface receives data from said MAC controller and/or when said interface receives data from said PHY device.

17. The system according to claim 1, wherein said MAC controller is operable to generate said dummy data.

18. The system according to claim 7, wherein said PHY device is operable to discard said dummy data when said dummy data is received by said PHY device.

19. The system according to claim 1, wherein said PHY device is operable to generate said dummy data.

20. The system according to claim 9, wherein said MAC controller is operable to discard said dummy data when said dummy data is received by said MAC device.

11. A system for networking, the system comprising:

one or more circuits for use in a communication device, said one or more circuits comprising a MAC controller, a PHY device, and an interface that enables communication between said MAC controller and said PHY device, wherein;

said interface is configurable to operate in an energy saving mode; and

while said interface is operating in said energy saving mode, said interface is operable to maintain synchronization between said MAC controller and said PHY device by one or both of adjusting a clock generated for said interface and/or communicating dummy data via said interface.