SYSTEM AND METHOD FOR INTEGRATED CIRCUIT CALIBRATION

• US 20090259425A1
• Filed: 04/10/2008
• Published: 10/15/2009
• Est. Priority Date: 04/10/2008
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Ku, Ting, Smith, Brian, Yu, Shifeng
• Granted Patent: US 8,793,091 B2
• Time in Patent Office: Days
• US Class Current: 702/104
• CPC Class Codes: G01K 15/00 Testing or calibrating of thermometers
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching

Abstract

A system and method for calibrating an integrated circuit. The method includes configuring a first impedance for a first output of the integrated circuit according to a first configuration code and measuring a first voltage at the first output which corresponds to the first configuration code. The method further includes configuring a second impedance for a second output of the integrated circuit according to a second configuration code and measuring a second voltage at the second output which corresponds to the second configuration code. A determination of which of the first voltage and the second voltage is nearest to a predetermined voltage value. Based on the voltage determination, the integrated circuit is configured according a code of said first and second codes that corresponds to the voltage nearest to the predetermined voltage.

Claims

1. A method for calibrating an integrated circuit, comprising:

configuring a first impedance for a first output of said integrated circuit according to a first configuration code;

measuring a first voltage at said first output, wherein said first voltage corresponds to said first configuration code;

configuring a second impedance for a second output of said integrated circuit according to a second configuration code;

measuring a second voltage at said second output, wherein said second voltage corresponds to said second configuration code;

determining which of said first voltage and said second voltage is nearest to a predetermined voltage value; and

configuring said integrated circuit according to a code of said first and second codes that corresponds to said voltage nearest to said predetermined voltage.

2. A method as described in claim 1 wherein said measuring of said first voltage and said second voltage is performed by an integrated circuit tester coupled to said integrated circuit.

3. A method as described in claim 1 wherein said configuring comprises blowing a fuse disposed with said integrated circuit that controls said first and second impedance.

4. A method as described in claim 3 wherein said fuse is coupled to a pull up circuit.

5. A method as described in claim 3 wherein said fuse is coupled to a pull down circuit.

6. A method as described in claim 1 wherein said first and second impedance for said first and second output is configured via a pull up circuits.

7. A method as described in claim 1 wherein said first and second impedance for said first and second output is configured via pull down circuits.

8. A method as described in claim 1 wherein said first and second output is a general purpose input/output (GPIO).

9. A method as described in claim 1 wherein said first code is part of a first set of codes and said second code is part of a second set of codes.

10. A system for calibrating an integrated circuit comprising:

an interface for coupling an integrated circuit to be calibrated;

an impedance configuration module operable to issue a first code and a second code to a first driver and a second driver, respectively, of said integrated circuit wherein said first code and said second code are associated with a first impedance value and a second impedance value of said first and second drivers of said integrated circuit;

a voltage measurer for measuring a first voltage and a second voltage at outputs of said first and second drivers of said integrated circuit;

a code determiner operable to determine which voltage of a first voltage corresponding to said first code and a second voltage corresponding to said second code is closer to a predetermined voltage; and

an integrated circuit configuration module operable to configure said first and second drivers of said integrated circuit according to said first code or said second code based on whether said first voltage or said second voltage is closest to said predetermined voltage.

11. The system of claim 10 wherein said code determiner determines a third code via interpolation.

12. The system of claim 10 wherein said first driver of said integrated circuit comprises a pull up circuit and wherein said impedance configuration module issues said first code to said pull up circuit.

13. The system of claim 12 wherein said integrated circuit configuration module configures said integrated circuit by blowing a fuse coupled to said pull up circuit.

14. The system of claim 10 wherein said first driver of said integrated circuit comprises a pull down circuit and wherein said impedance configuration module issues said first code to said pull down circuit.

15. The system of claim 14 wherein said integrated circuit configuration module configures said integrated circuit by blowing a fuse coupled to said pull down circuit.

16. The system of claim 10 wherein at least one output of said integrated circuit is a general purpose input output (GPIO).

17. A programmable system on a chip (SoC) comprising:

a plurality of outputs;

a plurality of drivers respectively coupled to said plurality of outputs, each driver comprising;

a pull up circuit coupled to a respective output;

a pull down circuit coupled to said respective output;

an impedance configuration circuit coupled to said pull up circuits and said pull down circuits of said plurality of drivers, wherein said impedance configuration circuits configures an impedance of each pull up circuit and each pull down circuit;

a fuse operable to fix the impedance configuration of all pull up circuits based on a calibration result performed on said SoC during testing; and

a fuse operable to fix the impedance configuration of each pull down circuits based on said calibration result.

18. A SoC as described in claim 17 further comprising a voltage and/or temperature sensor.

19. A SoC as described in claim 17 further comprises a GPU.

20. A SoC as described in claim 17 further comprises a video processor.