LOW-POWER RECONFIGURABLE ARCHITECTURE FOR SIMULTANEOUS IMPLEMENTATION OF DISTINCT COMMUNICATION STANDARDS
First Claim
1. A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms, comprising:
- a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and
a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols;
wherein at least some of the same megafunctions are used with algorithms of two or more protocols.
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Abstract
A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols.
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Citations
51 Claims
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1. A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms, comprising:
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a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols; wherein at least some of the same megafunctions are used with algorithms of two or more protocols. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. The chip architecture for use in processing signals encoded in accordance with any one of a plurality of protocols each defined by a series of algorithms, comprising:
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a plurality of megafunctions; a plurality of switches configured to selectively interconnect the necessary megafunctions for processing the signals encoded with each of the protocols; and memory for storing control signals applied to the switches as a function of the protocol of the signals to be processed. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A chip architecture comprising:
a controller for operating the plurality of switches so that different megafunctions can be interconnected to implement the same algorithm at the different stages in order provide efficient allocation of resources for implementing the protocol. - View Dependent Claims (40)
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41. A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms, comprising:
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an input/output for receiving input data and providing output processed data; memory for storing instructions relating to the configuration of the chip for each of the protocols; a plurality of megafunctions configured to be interconnected in each of plurality of configurations, at least one configuration corresponding to each of the communication protocols; a plurality of switches configured and responsive to control signals so as to interconnect the megafunctions in each of the plurality of configurations as determined by the communication protocol of the encoded signals; a reconfigurable net bus for interconnecting the switches, megafunctions and input/output; and a CPU configured to control the configuration of the megafunctions, switches and buses as a function of the communication protocol of the encoded signals. - View Dependent Claims (42, 43, 44, 45, 46)
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47. A wireless communication device for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms, comprising:
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an antenna for receiving and transmitting a signal encoded in accordance with anyone of a plurality of communication protocols; a baseband processor for processing the signals received and transmitted by the antenna; configware comprising; a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols; wherein at least some of the same megafunctions are used with algorithms of two or more protocols. - View Dependent Claims (48, 49, 50)
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51. A method of manufacturing a chip with an architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms, comprising creating configware so as to include:
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a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols; wherein at least some of the same megafunctions are used with algorithms of two or more protocols.
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Specification