METHOD AND APPARATUS FOR A VOLUME MANAGEMENT SYSTEM IN A NON-VOLATILE MEMORY DEVICE

• US 20090259799A1
• Filed: 04/11/2008
• Published: 10/15/2009
• Est. Priority Date: 04/11/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wong, Wanmo
• Granted Patent: US 9,477,587 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: H03M 13/1174 Parity-check or generator matrices built from sub-matrices representing known block codes such as, e.g. Hamming codes, e.g. generalized LDPC codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes

Abstract

Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. The memory system is partitioned to include a second addressable range of memory blocks capable of storing data indicating attributes of the first addressable range of memory blocks. The second addressable range of memory blocks may also be periodically updated such that the capacities of the first addressable range of memory blocks may be dynamically adjusted depending on application needs and changes to the non-volatile memory device over time. In some embodiments, one partition of a memory device may be configured for high reliability data storage while a second partition is configured for normal reliability storage.

Claims

1. A system for partitioning a non-volatile memory device comprising:

a first addressable range of memory blocks configured to store at least one type of data in at least one partitioned region; and

a second addressable range of memory blocks configured to store attribute data of the first addressable range of memory blocks, the second addressable range of memory blocks being configurable to update the attribute data, wherein updating the attribute data causes the at least one partitioned region of the first addressable range of memory blocks to be adjusted.

2. The system of claim 1 wherein the second addressable range of memory blocks comprise being adjusted responsive to a file management software.

3. The system of claim 1 wherein the at least one type of data stored in the first addressable range of memory blocks comprises data stored as one-bit data.

4. The system of claim 3 wherein the at least one type of data comprises software code, and at least another type of data comprises user data.

5. The system of claim 1 wherein the attribute data stored in the second addressable range of memory blocks comprises a bad block map to identify and locate bad memory blocks.

6. The system of claim 5 wherein the attribute data further comprises data to instruct and track wear-leveling and reclamation operations.

7. The system of claim 6 wherein the attribute data comprises data that includes bad block indicators, block type, number of erases, block identification, page identification, page count, partition count, raw volume assignments, and sector volume assignments.

8. The system of claim 1 wherein the at least one type of data and the attribute data comprise being stored with an error correcting code.

9. A non-volatile memory device comprising:

an array of memory cells arranged in rows and columns, the array of memory cells configurable to store either a single bit of data or multiple bits of data, wherein a predetermined number of cells configured to store the single bit of data and a predetermined number of cells configured to store the multiple bits of data is adjustable.

10. The non-volatile memory device of claim 9 wherein the predetermined number of cells configured to store the single bit of data comprises attribute data that represent attribute information of the non-volatile memory device.

11. The non-volatile memory device of claim 10 wherein the attribute data comprises data that includes bad block indicators, block type, number of erases, block identification, page identification, page count, partition count, raw volume assignments, and sector volume assignments.

12. The non-volatile memory device of claim 9 wherein the predetermined number of cells configured to store the single bit of data and the predetermined number of cells configured to store the multiple bits of data comprises data stored with an error correcting code.

13. The non-volatile memory device of claim 9 wherein the predetermined number of cells configured to store the single bit of data comprises software data, and the predetermined number of cells configured to store the multiple bits of data comprises user data.

14. A non-volatile memory device having a plurality of addressable memory blocks, the memory device comprising:

at least one memory block in a first group of memory blocks configurable to store data with a first reliability level;

at least one memory block in a second group of memory blocks configurable to store data with a second reliability level that is higher than the first reliability level; and

at least one memory block in a third group of memory blocks configurable to store attribute data of the first and second groups of memory blocks, and configurable to update the attribute data, wherein the updated attribute data causes the capacity of the first group of memory blocks and the capacity of the second group of memory blocks to be adjusted.

15. The memory device of claim 14 wherein the third group of memory blocks comprising:

a marker block configured to separate the third group of memory blocks from the first and second group of memory blocks;

at least one data block configured to store data that represent attributes of the first and second group of memory blocks; and

at least one spare data block configured to store a copy of the data from the at least one data block during a data update operation.

16. The memory device of claim 14 wherein the capacity of the first group of memory blocks and the capacity of the second group of memory blocks being adjusted comprises changing the number of blocks assigned to the first group of memory blocks and the number of memory blocks assigned to the second group of memory blocks.

17. The memory device of claim 14 wherein the data stored with the first reliability level comprises data stored in multi-level memory cells, and wherein the data stored with the second reliability level comprises data stored in single-level memory cells.

18. The memory device of claim 17 wherein the data stored in the single-level memory cells comprise software code, and wherein the data stored in the multi-level memory cells comprise user data.

19. The memory device of claim 14 wherein the third group of memory blocks is configured to store attribute data in single-level memory cells.

20. The memory device of claim 14 wherein the third group of memory blocks comprises storing attribute data that includes a bad block map to identify and locate bad memory blocks.

21. The memory device of claim 14 wherein the third group of memory blocks comprises data that includes bad block indicators, block type, number of erases, block identification, page identification, page count, partition count, raw volume assignments, and sector volume assignments.

22. The memory device of claim 14 wherein the data stored with the first reliability level comprises data stored with Hamming codes as an error correcting code, and the data stored with the second reliability level comprises data stored with BCH codes as the error correcting code.

23. A NAND FLASH memory device comprising:

a first array of NAND structured memory cells, the first array of NAND structured memory cells configurable to store multiple bits of data; and

a second array of NAND structured memory cells, the second array of NAND structured memory cells configurable to store a single bit of data, wherein a predetermined portion of the second array of NAND structured memory cells are selected to store attribute information of the NAND FLASH memory device, the predetermined portion of the second array being configurable to update and adjust the first and second arrays of the NAND structured memory cells.

24. The NAND FLASH memory device of claim 23 wherein the attribute information comprises a partition map of the first and second arrays of the NAND structured memory cells and of the data contained in the first and second arrays.

25. The NAND FLASH memory device of claim 24 wherein the attribute information comprises information that includes bad block indicators, block type, number of erases, block identification, page identification, page count, partition count, raw volume assignments, and sector volume assignments.

26. The NAND FLASH memory device of claim 23 wherein either the single bit of data or the multiple bits of data comprises error correcting code bits as data bits.

27. The NAND FLASH memory device of claim 23 wherein the single bit of data comprises software data, and the multiple bits of data comprises user data.

28. A memory system comprising:

a plurality of memory devices, each memory device having at least one memory block configurable to store either a first data type with a normal memory storage reliability or a second data type with a high storage reliability; and

at least one memory device configured to store attribute data of the plurality of memory devices, the at least one memory device operable to track updates to the plurality of memory devices in a centralized location and to update the attribute data in a manner that changes the assigned data type of the at least one memory block to either the normal storage reliability or the high storage reliability.

29. The memory system of claim 28 wherein the at least one memory block configurable to store the first data type with the high storage reliability comprises single-level memory cells, and wherein the at least one memory block configurable to store the second data type with the normal memory storage reliability comprises multi-level memory cells.

30. The memory system of claim 29 wherein the data stored in the single-level memory cells comprise software code, and wherein the data stored in the multi-level memory cells comprise user data.

31. The memory system of claim 28 wherein the attribute data stored in the centralized location is stored in single-level memory cells.

32. The memory system of claim 28 wherein the at least one memory device configured to store attribute data of the plurality of memory devices comprises:

a marker block configured to differentiate the centralized location from either the first or second type of memory blocks in the at least one memory device;

at least one data block configurable to store attribute data; and

at least one spare data block configurable to store data when the at least one data block is occupied.

33. The memory system of claim 32 wherein the attribute data comprises data that includes bad block indicators, block type, number of erases, block identification, page identification, page count, partition count, raw volume assignments, and sector volume assignments.

34. A system comprising:

a processor operable to process data and to provide memory commands and addresses to request read data or instruct write data;

an input device coupled to the processor;

an output device coupled to the processor; and

a non-volatile memory device coupled to the processor and operable to receive the read request or the write instruction from the processor, the non-volatile memory comprising;

a first addressable range of memory blocks configured to store at least one type of data received from the processor in at least one partitioned region; and

a second addressable range of memory blocks configured to store attribute data of the first addressable range of memory blocks, the second addressable range of memory blocks being configurable to update the attribute data, wherein updating the attribute data causes the at least one partitioned region of the first addressable range of memory blocks to be adjusted.

35. The system of claim 34 wherein the memory device is configured to receive command signals and address signals from the processor, and operable to read data from the memory device, write data to the memory device, and update data on the memory device responsive to the command and address signals.

36. The system of claim 34 wherein the at least one type of data stored in first addressable range of memory blocks comprises data stored as one-bit data.

37. The system of claim 34 wherein the second addressable range of memory blocks comprises being configurable to store the attribute data as one-bit data.

38. The system of claim 34 wherein the attribute data stored in the second addressable range of memory blocks comprises a bad block map to identify and locate bad memory blocks.

39. The system of claim 38 wherein the attribute data further comprises data to instruct and track wear-leveling and reclamation operations in response to commands from the processor.

40. The system of claim 34 wherein the second addressable range of memory blocks further comprises:

a marker block configured to differentiate the second addressable range of memory blocks from the first addressable range of memory blocks;

at least one data block configured to store the attribute data; and

at least one spare block configured to store data when the at least one data block is occupied.

41. The system of claim 40 wherein the attribute data stored in the at least one data block comprises data that includes bad block indicators, block type, number of erases, block identification, page identification, page count, partition count, raw volume assignments, and sector volume assignments.

42. The system of claim 34 wherein the second addressable range of memory blocks further comprises being configurable to update the stored attribute data in response to memory commands and addresses from the processor, and to dynamically adjust the partitioned regions of the first addressable range of memory block responsive to the update.

43. A consumer device comprising:

a processor operable to process data, addresses, control commands, and memory commands; and

a user input device coupled to the processor, the user input device comprising a non-volatile memory device comprising;

an array of memory cells arranged in rows and columns, the array of memory cells configurable to store either a single bit of data or multiple bits of data, wherein a predetermined number of cells configured to store the single bit of data and a predetermined number of cells configured to store the multiple bits of data comprises being adjustable.

44. The consumer device of claim 43 wherein the predetermined number of cells configured to store the single bit of data comprises data representing attribute information of the non-volatile memory device.

45. The consumer device of claim 44 wherein the attribute information comprises data including bad block indicators, block type, number of erases, block identification, page identification, page count, partition count, raw volume assignments, and sector volume assignments.

46. The consumer device of claim 43 wherein the non-volatile memory device comprises a NAND FLASH memory device operable to store data.

47. The consumer device of claim 46 wherein the predetermined number of cells configured to store the single bit of data comprises software data, and the predetermined number of cells configured to store the multiple bits of data comprises user data.

48. The consumer device of claim 47 further comprising a display screen coupled to the processor, the display screen configurable to display an image stored as user data in the non-volatile memory device.

49. The consumer device of claim 47 wherein the user input device comprises a CMOS imager device configurable to store image data as user data and programming code as software data.

50. The consumer device of claim 47 wherein the user input device comprises an audio receiver/transmitter device configurable to store audio signal data as user data and programming code as software data.

51. A method of partitioning a memory device having data stored with different types of storage reliability, the method comprising:

storing attribute information of the partitioned regions in a centralized location of the memory device;

tracking changes to the data stored in the different types of storage reliability in the partitioned regions;

updating the attribute information in the centralized location of the memory device; and

adjusting the partitioned regions of the memory device responsive to updates to the attribute information.

52. The method of claim 51 wherein updating the attribute information comprises updating the attribute information responsive to instructions from a file management software.

53. The method of claim 51 wherein storing attribute information of the partitioned regions in the centralized location comprises storing the attribute information as data in single-level memory cells.

54. The method of claim 51 wherein storing attribute information of the partitioned regions comprises storing data that includes a bad block map to identify and locate bad memory blocks.

55. The method of claim 51 wherein storing attribute information of the partitioned regions comprises storing data to instruct and track wear-leveling and reclamation operations.

56. The method of claim 55 wherein storing attribute information of the partitioned regions comprises storing data that includes bad block indicators, block type, number of erases, block identification, page identification, page count, partition count, raw volume assignments, and sector volume assignments.

57. The method of claim 51 wherein storing attribute information of the partitioned regions comprises storing data with an error correcting code.

58. The method of claim 51 wherein adjusting the partitioned regions of the memory device comprises changing the type of storage reliability responsive to the updated attribute information.

59. A method of storing data on a memory device comprising:

storing data with a first reliability level in a first region of the memory;

storing data with a second reliability level that is higher than the first reliability level in a second region of memory; and

adjusting the stored data in the first region and the stored data in the second region.

60. The method of claim 59 further comprising storing and updating attribute data of the first and second regions of memory in a third region of memory.

61. The method of claim 60 wherein storing and updating attribute data comprises:

storing attribute data in at least one data block within the third region of memory;

copying the attribute data with updates onto at least one spare block within the third region of the memory; and

erasing the originally stored attribute data in the at least one data block.

62. The method of claim 61 further comprising marking the third region of memory to differentiate the third region of memory from the first and second regions of memory.

63. The method of claim 62 wherein the attribute data in the third region of memory are stored in single-level memory cells.

64. The method of claim 60 wherein storing and updating the attribute data comprises storing and updating data that includes a bad block map to identify and locate bad memory blocks.

65. The method of claim 64 wherein storing and updating the attribute data comprises storing and updating data to instruct and track wear-leveling and reclamation operations.

66. The method of claim 65 wherein storing and updating the attribute data comprises storing and updating data that includes bad block indicators, block type, number of erases, block identification, page identification, page count, partition count, raw volume assignments, and sector volume assignments.

67. The method of claim 59 wherein storing data with the first reliability level in the first region of memory comprises storing data in multi-level memory cells, and wherein storing data with the second reliability level in the second region of memory comprises storing data in single-level memory cells.

68. The method of claim 67 wherein storing data in the single-level memory cells comprises storing software code, and wherein storing data in the multi-level memory cells comprises storing user data.

69. The method of claim 67 wherein the data stored in the single-level memory cells comprises data stored using BCH codes as an error correcting code, and the data stored in the multi-level memory cells comprises data stored using Hamming codes as an error correcting code.